AXI Knowledge Articles

Knowledge Articles in this section

• Are there any issues related to hazard detection on overlapping locations?
• Are there any issues with exclusive accesses passing from one width of data bus to another?
• Are there any recommendations about the types of accesses that are used for atomic accesses?
• Are there any recommendations for verifying AXI components?
• At what point can the master consider that the transaction has been accepted by the slave such that the responsibility for hazard checking lies with the slave?
• Can BVALID be asserted before WLAST in a write transaction?
• Can a master change the control signals for different transactions in a locked sequence?
• Can an exclusive access use sparse write data strobes?
• Can an unlocking transaction be an exclusive access?
• Can the WVALID signal for a write transfer be active before the AWVALID? If so, how does the interconnect know which slave the transfer is for?
• Can write responses be re-ordered in the same way that read data can be re-ordered?
• Does a master always have to perform the write portion of an exclusive access?
• How can a slave return a BRESP before knowing the AWADDR value for the transaction ?
• How do you calculate addresses used in WRAP type bursts?
• How do you ensure interoperability between AXI components?
• How does a SWP operation on a CPU translate in to bus activity?
• How important is it that a sequence of locked transactions does not cross a 4k byte boundary?
• How should a 32-bit write accesses across a 64-bit bus be represented as AXI transactions?
• How should a bridge deal with an AXI transfer that is marked as non-secure and bufferable?
• If BRESP indicates an error, does that mean that none of the transaction's data was written to memory?
• If a slave receives three addresses from different masters M1, M2 and M3 in that order and has an interleaving depth of 3 can the slave expect to see any data from M3 before it sees data from masters M1 and M2?
• Should a slave respond with an error or OKAY response when the user addresses memory space in the slave that has no registers?
• Should slaves/bridges which have some form of write buffer capability also include forwarding logic to return the result of a read transaction when a write to the same location is stored in the write buffer?
• Should the protection/cache information for address regions be consistent between read and write operations?
• The specification mentions that AxPROT[2] information is just a hint. Is the information given by the other AxPROT bits always accurate?
• What AXI response value should be given by a slave which contains a mixture of secure and non-secure registers, when a non-secure access is attempted to a secure register?
• What AXI response value should be given to a non-secure access to a secure address location?
• What are the allowable byte lane strobes for fixed address burst?
• What happens if the slave is keeping AWREADY low waiting for the write response to be accepted while the master is keeping BREADY low waiting for the address to be accepted by the slave?
• What is meant by the arrows in section 3.3, "Dependencies between the channel handshake signals"?
• What is the ACLKEN signal?
• When a master has issued a locked transfer with one ID can it start a different locked transfer with a different ID?
• When an interconnect adds bits to the ID field does it add high-order bits or low-order bits?
• When can a master consider a write transaction complete, when it is trying to determine which write data sources it can interleave?
• When there are several bursts with same ID to a slave, are they counted separately or as one in regard to the write data interleaving-depth of the slave?
• Why are the read and write address buses defined with all four bits of ACACHE. Does a read transaction need to give the write allocate information and vice versa?
• Why is AXI spec suitable for "high bandwidth" designs ?
• Why is the READY signal not sticky?
• Why is the VALID signal described as "sticky"?
• Why is the VALID signal sticky?