Cortex-M3 Knowledge Articles

Knowledge Articles in this section

• Are the Cortex-M3's INTISR signals synchronous or asynchronous?
• At what frequency can TRACECLKIN be run?
• Can Cortex-M3/4 have a pending Halt after Reset?
• Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
• Can I prevent my interrupt handlers from being interrupted?
• Can I set the MPU to prevent any further modification of the MPU settings?
• Can I use 16-bit memory for Thumb-2 code?
• Can a Cortex-M3/M4 check the contents of the ETM by reading the TPIU Integration Registers?
• Can the Cortex-M3 handle 'dynamic' endian switching?
• Cortex-M3 example_tbench simulation (run_example) in Mentor Modelsim/Questasim (MTI) produces duplicate lines in tarmac.log
• Describe late-arriving interrupt behaviour
• Does Cortex-M3 Support Coprocessors?
• Does Cortex-M3 need Memory Barrier instructions?
• Does the Cortex-M3 ETM support Cycle-Accurate Trace?
• Does the Cortex-M3 support ARM code?
• How are Memory Type and Memory Attributes represented on the AHB-Lite bus interfaces of Cortex-M3 and Cortex-M4?
• How can I check for Erratum 602117 LDRD opcodes in my Cortex-M3 code image?
• How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?
• How can a Cortex-M processor wake up from WFI if interrupts are masked or disabled?
• How do I boot an ARMv7-M processor with uninitialized memory at address zero?
• How do I control clock gating?
• How do I use the SETPEND and CLRPEND registers in Cortex-M3?
• How does Cortex-M3 handle 32-bit opcodes not aligned on word boundaries?
• How should I write to the System Handler Control and State Register?
• How to enter the debug state for Cortex-M3
• I cannot find the "Integration and Implementation Manual" (IIM) on infocenter.arm.com
• I don't understand the description of background region priority under PRIVDEFENA in the TRM
• Is there a risk in using processor-only reset (SYSRESETn) rather than full reset (PORESETn) in Cortex-M3?
• My test for memory Bus Fault gets stuck repeating the fault again and again
• Reads from DWT registers return unexpected values
• What are STCALIB and STCLKEN or STCLK, and how should I connect them in the SoC?
• What happens when the EDBGRQ signal is asserted?
• What is the purpose of the DEBUG_LVL and TRACE_LVL configuration parameters?
• Which ARMv7-M Special Registers may be accessed by MSR/MRS instructions?
• Why do I get a fault when I load a literal value and then branch to it?
• Why does my Cortex-M processor Lock Up with a Hard Fault a few cycles after reset?
• Why does the Cortex-M3 TRM imply that Cortex-M3 can fetch from Peripheral and External Device memory?
• Why is the SysTick Calibration TENMS value one less than the number of clock cycles required for 10ms?