ARM Technical Support Knowledge Articles
Cortex-M3 Knowledge Articles
Knowledge Articles in this section
Bus Interface (7)
"run_example" script fails to link "libmgmm.so" to 64-bit Verilog simulator
Accessing 64-bit peripherals using Cortex-M processors
Are the Cortex-M3's INTISR signals synchronous or asynchronous?
At what frequency can TRACECLKIN be run?
Bit-banded accesses versus read-modify-write accesses
Can Cortex-M3 / Cortex-M4 make a simultaneous instruction fetch and data access to Code space?
Can Cortex-M3/4 have a pending Halt after Reset?
Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
Can I prevent my interrupt handlers from being interrupted?
Can I set the MPU to prevent any further modification of the MPU settings?
Can I use 16-bit memory for Thumb-2 code?
Can I use both SWO Single Wire Output and the Parallel Trace Port for trace?
Can a Cortex-M3/M4 check the contents of the ETM by reading the TPIU Integration Registers?
Can the Cortex-M3 handle 'dynamic' endian switching?
Cortex-M3 example_tbench simulation (run_example) in Mentor Modelsim/Questasim (MTI) produces duplicate lines in tarmac.log
Describe late-arriving interrupt behaviour
Does Cortex-M3 Support Coprocessors?
Does Cortex-M3 need Memory Barrier instructions?
Does Cortex-M3 or Cortex-M4 provide status information to distinguish between cold and warm reset?
Does the Cortex-M3 ETM support Cycle-Accurate Trace?
Does the Cortex-M3 support ARM code?
How are Memory Type and Memory Attributes represented on the AHB-Lite bus interfaces of Cortex-M3 and Cortex-M4?
How can I check for Erratum 602117 LDRD opcodes in my Cortex-M3 code image?
How can I count the number of instructions executed by the processor in a given time interval?
How can I ensure that WFE causes sleep?
How can I use the SWJIM which comes with Cortex-M3 for my chip-level design?
How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?
How can a Cortex-M processor wake up from WFI if interrupts are masked or disabled?
How can software identify one Cortex-M3/4 processor instance in a SoC containing multiple instances?
How do I boot a Cortex-M3 or Cortex-M4 processor with uninitialized memory at address zero?
How do I control clock gating?
How do I use the SETPEND and CLRPEND registers in Cortex-M3?
How does Cortex-M3 and Cortex-M4 conform to the ARMv7-M Architecture for Load and Store Exclusives?
How does Cortex-M3 handle 32-bit opcodes not aligned on word boundaries?
How does the DMIPS/MHz performance vary with wait-states on the code memory?
How flexible is the interrupt and excpetion priority scheme in ARMv7-M?
How should I write to the System Handler Control and State Register?
How to access a Cortex-M processor's memory system from my own Debug transactor?
How to enter the debug state for Cortex-M3
I cannot find the "Integration and Implementation Manual" (IIM) on infocenter.arm.com
I don't understand the description of background region priority under PRIVDEFENA in the TRM
IIM description of HMASTERD = 0b10 does not make sense
In DAPML, what is the difference between DAP_READ_AP / DAP_WRITE_AP and DAP_READ_APACC / DAP_WRITE_APACC
Is there a risk in using processor-only reset (SYSRESETn) rather than full reset (PORESETn) in Cortex-M3?
Is there a simple way to measure the execution performance of arbitrary code in simulation?
My test for memory Bus Fault gets stuck repeating the fault again and again
Reads from DWT registers return unexpected values
Serial Wire Debug sequence fails to produce WAIT responses for wait-states then generates WDATAERR
The ARMv7-M ARM describes address 0xE000E000 as the SCS, but the TRM and IIM describe it as the NVIC. Which is it?
Unable to access TPIU registers, they appear to be stuck at zero
Unable to program the Data Watchpoint Unit / Data Watchpoint and Trace Unit (DWT)
Unexpected memory behavior at addresse ranges 0x22xxxxxx, 0x23xxxxxx, 0x42xxxxxx or 0x43xxxxxx
What AHB-Lite burst lengths are produced by Cortex-M3 and Cortex-M4?
What are STCALIB and STCLKEN or STCLK, and how should I connect them in the SoC?
What happens when the EDBGRQ signal is asserted?
What is CTIINTISR[1:0]?
What is the difference between DAPEN and DBGEN?
What is the effect of DAPABORT?
What is the purpose of the DEBUG_LVL and TRACE_LVL configuration parameters?
What is the true interrupt latency of Cortex-M3 and Cortex-M4 for interrupt entry and exit?
Which AHB-Lite BURST and TRANSFER types are produced by Cortex-M3 and Cortex-M4?
Which ARMv7-M Special Registers may be accessed by MSR/MRS instructions?
Why do I get a fault when I load a literal value and then branch to it?
Why does my Cortex-M processor Lock Up with a Hard Fault a few cycles after reset?
Why does the Cortex-M3 TRM imply that Cortex-M3 can fetch from Peripheral and External Device memory?
Why is the SysTick Calibration TENMS value one less than the number of clock cycles required for 10ms?
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