ARM Technical Support Knowledge Articles
ARM966E-S Knowledge Articles
Knowledge Articles in this section
Bus Interface (6)
Cache and Write Buffer (2)
Reset and Initialization (3)
Are the IRQ and FIQ interrupts level-sensitive?
Are there are any special considerations when memory mapping hardware registers?
Can we supply the RTL of the ARM cores to our customer or EDA vendors?
Do I need to implement byte-write access on the ITCM?
Do I need to keep the clock running when the reset line is asserted?
How can the ARM banked registers be initialized?
I'm not implementing an external coprocessor. How should I tie off the interface?
If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
Is RTCK required as a dedicated output?
Is a DesignWare foundation license required to synthesize the ARM synthesizable cores?
Is there a priority scheme for exceptions?
Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
What AHB transactions will my ARM core generate?
What are the differences between the AHB Interfaces of the ARM9E family cores?
What differences are there between the ARM968E-S and the ARM966E-S (Rev 2) ?
What do I set the ARM TAP IDCODE to?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens inside the ARM core when an exception occurs?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the test strategy for ARM soft cores?
What kind of bursts will the ARM966E-S perform?
What values are in ARM registers after a power-on reset?
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