ARM Technical Support Knowledge Articles
ARM1026EJ-S Knowledge Articles
Knowledge Articles in this section
Bus Interface (4)
Cache and Write Buffer (3)
Reset and Initialization (3)
Are the IRQ and FIQ interrupts level-sensitive?
Are there are any special considerations when memory mapping hardware registers?
Can we supply the RTL of the ARM cores to our customer or EDA vendors?
Do I need to keep the clock running when the reset line is asserted?
How can the ARM banked registers be initialized?
If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
Is RTCK required as a dedicated output?
Is a DesignWare foundation license required to synthesize the ARM synthesizable cores?
Is there a priority scheme for exceptions?
Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
What AHB transactions will my ARM core generate?
What are imprecise aborts ?
What do I set the ARM TAP IDCODE to?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens inside the ARM core when an exception occurs?
What is the advantage of using the core VIC port ?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the function of the Issue stage in the ARM10/ARM11 cores ?
What is the test strategy for ARM soft cores?
What values are in ARM registers after a power-on reset?
Which cached cores are available and what do they include?
Link to this index
Copyright © 2011 ARM Limited. All rights reserved.