ARM Technical Support Knowledge Articles
Cortex-A7 Knowledge Articles
Knowledge Articles in this section
Can non 64B aligned WRAP4 write transfers occur on Cortex-A7 ?
Can you explain the generic timer architecture on Cortex-A7 and Cortex-A15 ?
Performance Monitor Unit example code for ARM11 and Cortex-A/R
The L2 data RAM clock becomes X during MBIST mode.
What is the Cortex-A7âs behavior if we turn-on the L1/L2 data cache read-allocate mode disable bits ?
What kind of unaligned AMBA access can Cortex-A7 generate ?
Why do Cortex-A7 and Cortex-A15 behave differently when handling WFE instructions ?
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