ARM7EJ-S Knowledge Articles

Knowledge Articles in this section

• Are the IRQ and FIQ interrupts level-sensitive?
• Are there are any special considerations when memory mapping hardware registers?
• Can the java instructions be disabled for ARM7EJ-S?
• Can we supply the RTL of the ARM cores to our customer or EDA vendors?
• Do I need to keep the clock running when the reset line is asserted?
• Does the ARM7EJ-S support logical equivalence?
• How can the ARM banked registers be initialized?
• Is RTCK required as a dedicated output?
• Is a DesignWare foundation license required to synthesize the ARM synthesizable cores?
• Is a partner required to produce a Test Chip for the ARM7EJ-S?
• Is there a VHDL source release available for ARM7EJ-S?
• Is there a priority scheme for exceptions?
• We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
• What do I set the ARM TAP IDCODE to?
• What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
• What happens inside the ARM core when an exception occurs?
• What is the die size and how fast will the ARM7EJ-S run?
• What is the difference between a von Neumann architecture and a Harvard architecture?
• What is the fault coverage figure for ARM7EJ-S?
• What is the gate count figures for ARM7EJ-S?
• What is the test procedure for ARM7EJ-S?
• What is the test strategy for ARM soft cores?
• What is the total number of flip-flops in ARM7EJ-S?
• What sort of system bus does the ARM7EJ-S have?
• What values are in ARM registers after a power-on reset?
• Which tools are required to synthesize the ARM7EJ-S?