ARM Technical Support Knowledge Articles
ARM7TDMI Knowledge Articles
Knowledge Articles in this section
Bus Interface (12)
Reset and Initialization (6)
According to the TRM, nMREQ is only deasserted (to '1') preceding an Internal or coprocessor cycle. Why is it deasserted during an LDR instruction?
After executing a BX instruction to change into Thumb state, the ARM7TDMI is outputting addresses with A set. Why is this?
Are the IRQ and FIQ interrupts level-sensitive?
Are there are any special considerations when memory mapping hardware registers?
Are there special TCK considerations (like adaptive clocking) when the core is used within an AHB wrapper?
Can I use JTAG production test vectors for rev1 ARM7TDMI on a rev3 ARM7TDMI?
Can production test vectors be used to determine the maximum core speed of the ARM?
Do I need to keep the clock running when the reset line is asserted?
Do the test vectors check the TAP controller ID code?
During AMBA test some signals toggle unpredictably. Why is this?
How are the uni-directional data buses in the ARM7TDMI used?
How can I disable JTAG debug?
How can I replay the ARM7TDMI serial test patterns on the DSM?
How can the ARM banked registers be initialized?
How do I add scan chains to the ARM TAP controller?
How does Little / Big Endian mode affect aligned / unaligned addressing?
How does the coprocessor interface of the ARM7TDMI work?
How does the insertion of the AHB wrapper affect the performance of the ARM7TDMI?
How does the interrupt handling latency of the ARM720T compare with ARM7TDMI?
How does the memory controller know whether the current access is aligned/non aligned word/half-word/byte?
How is the ARM7TDMI core tested?
How should ARM7TDMI/ARM9TDMI pins be driven to test the core using serialised test vectors via JTAG?
How should power-on reset be applied to the ARM7TDMI?
If I connect DBGEN to '0' on ARM7TDMI, does this disable all debug functionality?
Is an internal (I) cycle always followed by a sequential (S) cycle?
Is there a priority scheme for exceptions?
Is there any method of at-speed testing for ARM7TDMI?
The ARM core itself has a lot of debug pins which are not routed out of the ARM AHB wrapper block (e.g. EXTERN, RANGEOUT, DBGACK, BREAKPT,...). Are they really necessary or is it sufficient to use the JTAG port only?
We saw that the ARM7TDMI has two address bus connections. Do these pins need to be connected in layout or is a connection to a single pin enough?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
We want to verify the (JTAG) debug system of the core in our simulation environment. Are there any prewritten test vectors/test benches available?
What are the considerations when designing with an ARM hard macro clock?
What are the differences between the ARM7TDMI-S and the ARM7TDMI?
What are the timing requirements of interrupts entering the ARM core?
What do I set the ARM TAP IDCODE to?
What do each of the ARM7TDMI production test patterns cover?
What does the ARM7TDMI core read/write when using non aligned addresses?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens if an interrupt occurs as it is being disabled?
What happens if an interrupt occurs as it is being enabled?
What happens inside the ARM core when an exception occurs?
What is the ARM7TDMI Serialised Test Procedure?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the timing relationship between TDI/SDIN and TDO/SDOUTBS?
What might an initial configuration of the ARM7TDMI look like?
What state does MCLK need to be when nRESET is taken low?
What values are in ARM registers after a power-on reset?
When must the ABORT signal become active to signal a data abort or a prefetch abort?
Why do you supply both min and max Synopsys .lib files for a particular process corner?
Why is the ARM720's Dhrystone MIPS rating lower than that of the ARM7TDMI?
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