ARM Technical Support Knowledge Articles
PL340 AXI SDRAM Controller Knowledge Articles
Knowledge Articles in this section
Can I change the value of msync and async after the power supply is turned on?
Can I connect my own DDR PHY with ARM PL34X DDR Memory controllers or is it restricted only to ARM Artisan DDR PHY?
Can PL340 support 512MByte memory?
Can we use delay cell instead of pad to reduce the number of Pads in ASIC design?
How can I reconfigure PL340 after reset?
How does the PL340 generate memory address from the AXI address?
How to generate CLK# pin in PL340 for DDR Memories?
If aclk is synchronous to mclk in our design, should the false paths between these clock domains in pl340_dmc_compile.tcl be removed?
In PL340 what is the difference between stop_mem_clk and auto_power_down?
Is it enough for the system clock controller to only monitor csysack of PL340 to know whether PL340 has acknowledged the low power request on csysreq?
Is there a restriction between aclk and mclk in asynchronous mode?
PL340 has a new cclken signal as part of its AXI C interface. What does this signal do?
There is a feature called "Deep Power Down" with Mobile SDRAM which cuts the power off the memory cells in Mobile SDRAM. Is this feature supported with PL340?
What is the correct value of "chip_nmbr" bits in direct cmd register to enter DPD state of all memory devices simultaneously with global CKE configuration?
What is the purpose of the ap_bit on PL340?
Link to this index
Copyright © 2011 ARM Limited. All rights reserved.