ARM Technical Support Knowledge Articles
ARM7TDMI-S Knowledge Articles
Knowledge Articles in this section
Bus Interface (2)
Reset and Initialization (3)
Are the IRQ and FIQ interrupts level-sensitive?
Are there are any special considerations when memory mapping hardware registers?
Can the ARM7TDMI-S accept asynchronous interrupts?
Can we supply the RTL of the ARM cores to our customer or EDA vendors?
Do I need to keep the clock running when the reset line is asserted?
How can the ARM banked registers be initialized?
Is RTCK required as a dedicated output?
Is a DesignWare foundation license required to synthesize the ARM synthesizable cores?
Is there a priority scheme for exceptions?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
What are the differences between the ARM7TDMI-S and the ARM7TDMI?
What do I set the ARM TAP IDCODE to?
What does "TDMI-S" stand for?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens inside the ARM core when an exception occurs?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the test strategy for ARM soft cores?
What values are in ARM registers after a power-on reset?
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