ARM Technical Support Knowledge Articles
ARM720T Knowledge Articles
Knowledge Articles in this section
Bus Interface (8)
Cache and Write Buffer (9)
Models/Design Sign-off Model (1)
Reset and Initialization (4)
Rev 0-3 (42)
Rev 4 (7)
Are the IRQ and FIQ interrupts level-sensitive?
Are there ARM720T core test vectors in JTAG serial test format?
Are there any known problems with the BERROR signal? (Rev 0-3)
Are there are any special considerations when memory mapping hardware registers?
Can a piece of code be locked into the cache?
Can the MMU set a piece of memory space (SDRAM) to read only?
Do I need to keep the clock running when the reset line is asserted?
Does the ARM720T with AHB wrapper use halfword or byte burst transfers? (Rev 0-3)
Does the ARM720T with the cache disabled behave like an ARM7TDMI?
Does the timing description of the ARM720T include arcs for when the device is selected as a slave for TIC testing?
Does using the ARM720T FASTBUS mode give significant performance improvement?
During AMBA test some signals toggle unpredictably. Why is this?
During our simulation we see a hold time violation on nIRQ relative to BCLK. Is it worth synchronizing nIRQ (and nFIQ) to BCLK externally? What happens when the ARM720T is running off FCLK?
During simulation we found that the AHB Wrapper HTRANS signal changes both on positive and negative clock edges, but the AHB is a single edge protocol. Why does the wrapper do this? (Rev 0-3)
How can I access the 720T CP15 registers by JTAG debug sequences?
How can I generate a simple page table for the ARM720T, so that I can turn on the MMU?
How can the ARM banked registers be initialized?
How do I add scan chains to the ARM TAP controller?
How do I drive FCLK during TIC testing of ARM720T?
How does Little / Big Endian mode affect aligned / unaligned addressing?
How does the interrupt handling latency of the ARM720T compare with ARM7TDMI?
How does the switching between BCLK and FCLK work in ARM720T?
If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
In the ARM720 Technical Reference Manual chapter, it is stated that the write buffer can hold up to 8 words of data and 4 independent addresses. Why is this?
Is it acceptable to concatenate all of the ARM720T TIF patterns to form one long file and run them all at once, with only one reset?
Is the cache in ARM720T a write through cache or a write back one?
Is there a C program which could build a default page table?
Is there a priority scheme for exceptions?
Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
The ARM720T has both nOPC and BPROT signals. According to the datasheet, both indicate opcode fetches. What is the difference between the two signals and what are they used for? (Rev 0-3)
There is a new signal for ARM720T rev 3, called CACHEDIS. How should I use this?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
What are the considerations when designing with an ARM hard macro clock?
What are the differences in the revisions of the ARM720T?
What do I set the ARM TAP IDCODE to?
What does it mean when the ARM720T model warns of an "Output violation"?
What does the ARM720T do when the cache is not enabled?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens inside the ARM core when an exception occurs?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the implication of not balancing FCLK and HCLK when I lay out my ARM720T design? Are there any implications for synchronous and asynchronous clocking modes?
What is the minimum time to hold BnRES low on the ARM720T to correctly reset the core?
What is the timing relationship between TDI/SDIN and TDO/SDOUTBS?
What values are in ARM registers after a power-on reset?
What will happen on a write-miss to a cacheable location?
Which cached cores are available and what do they include?
Why can't I get the ARM720T TIC patterns to pass in my simulation?
Why do you supply both min and max Synopsys .lib files for a particular process corner?
Why is the ARM720's Dhrystone MIPS rating lower than that of the ARM7TDMI?
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