ARM1136 Knowledge Articles

Knowledge Articles in this section

• Are the IRQ and FIQ interrupts level-sensitive?
• Are there are any special considerations when memory mapping hardware registers?
• Can I use my ARM926 code for an ARM11 core ?
• Do I need to keep the clock running when the reset line is asserted?
• How can the ARM banked registers be initialized?
• If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
• Is there a priority scheme for exceptions?
• Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
• We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
• What AHB transactions will my ARM core generate?
• What are imprecise aborts ?
• What are the AHB interfaces ?
• What do I set the ARM TAP IDCODE to?
• What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
• What happens inside the ARM core when an exception occurs?
• What is low latency mode ?
• What is the Peripheral Port Remap Register for ?
• What is the advantage of using TEX remapping ?
• What is the advantage of using super sections ?
• What is the advantage of using the LDREX,STREX ARM V6 instructions for semaphore operations over a SWP ?
• What is the advantage of using the core VIC port ?
• What is the difference between a von Neumann architecture and a Harvard architecture?
• What is the function of the Issue stage in the ARM10/ARM11 cores ?
• What is the performance of the branch prediction logic ?
• What is the test strategy for ARM soft cores?
• What values are in ARM registers after a power-on reset?
• Which cached cores are available and what do they include?
• Why does the core pipeline have 2 fetch stages ?
• Why have memory types been defined in the ARM V6 ISA ?