ARM9TDMI Knowledge Articles

Knowledge Articles in this section

• Are the IRQ and FIQ interrupts level-sensitive?
• Are there are any special considerations when memory mapping hardware registers?
• Do I need to keep the clock running when the reset line is asserted?
• How can the ARM banked registers be initialized?
• How do I add scan chains to the ARM TAP controller?
• How does Little / Big Endian mode affect aligned / unaligned addressing?
• How should ARM7TDMI/ARM9TDMI pins be driven to test the core using serialised test vectors via JTAG?
• I'm not implementing an external coprocessor. How should I tie off the interface?
• In which direction do the debug scan chains scan?
• Is there a priority scheme for exceptions?
• We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
• What are the considerations when designing with an ARM hard macro clock?
• What are the timing requirements of interrupts entering the ARM core?
• What do I set the ARM TAP IDCODE to?
• What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
• What happens inside the ARM core when an exception occurs?
• What is the difference between a von Neumann architecture and a Harvard architecture?
• What is the timing relationship between TDI/SDIN and TDO/SDOUTBS?
• What might an initial configuration of the ARM9TDMI look like?
• What values are in ARM registers after a power-on reset?