ARM Technical Support Knowledge Articles
AHB Knowledge Articles
Knowledge Articles in this section
* Does HWDATA have to remain stable during an extended transfer? *
AHB Protocol: Must a read after a write to the same address return the newly written data?
AHB-lite - Can HWDATA change in the 2nd cycle of an ERROR response ?
Arbitration: Can a master deassert HLOCK during a burst?
Arbitration: Can a master perform transfers other than IDLE when the bus was granted to it, but not requested by the master?
Arbitration: If a master is currently granted the bus by default, how many cycles before starting an non-IDLE transfer does it have to assert HBUSREQ?
Arbitration: What is the relationship between the HLOCK signal and the HMASTLOCK signal?
Arbitration: When can the HGRANT signal change?
Arbitration: Why is HADDR sometimes shown as an input to the arbiter?
Can an arbiter be designed to always allow bursts to complete?
Does a master need to issue non-LOCKed accesses when accessing a sequence of AHB slaves ?
Does the AHB Arbiter require address lines as input?
General : What system support is required if a slave can be powered down or have its clock stopped?
General : When can Early Burst Termination occur
General: Can HTRANS change whilst HREADY is low?
General: Can a BUSY transfer occur at the end of a burst?
General: Can a master change the address/control signals during a waited transfer?
General: Can an AHB master be connected directly to an AHB slave?
General: Do all slaves have to support the BUSY transfer type?
General: Does the address have to be aligned, even for IDLE transfers?
General: How many masters can there be in an AHB system?
General: How should AHB to APB bridges handle accesses that are not 32-bits?
General: Is HREADY an input or an output from slaves?
General: Is a default slave really necessary?
General: Is a dummy master really necessary?
General: Is it legal for a master to change HADDR when a transfer is extended?
General: Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?
General: The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed?
General: What are the different bursts used for?
General: What default state should be used for the HREADY and HRESP outputs from a slave?
General: What is a default slave?
General: What is the difference between a dummy bus master and a default bus master?
General: What is the recommended default value for HPROT?
General: What is the state of the AHB signals during reset?
General: What sequences of transfers types (HTRANS) can occur on the bus?
General: When a master rebuilds a burst which has been terminated early are there any limitations on how it rebuilds the burst?
General: Why is a burst not allowed to cross a 1 kilobyte boundary?
How do I use the ARMv6 AHB-Lite extension signals in my AMBA 2.0 system?
How do you connect an AHB Master to an AHB-lite system?
How do you connect an AHB slave to an AHB-lite system?
How do you connect an AHB-lite Master to a full AHB system?
How do you connect an AHB-lite Slave to a full AHB system?
How does AHB differ from AHB-lite?
How does the AHB handle LOCKed SPLITs?
How many clock cycles should the reset signal in an AMBA system be asserted for?
Is it legal for an AHB wrapping burst to be aligned with respect to the total number bytes in the burst, such that it does not wrap?
Split/Retry: Can a SPLIT or RETRY response be given at any point during a burst?
Split/Retry: Can a slave assert HSPLITx in the same cycle that it gives a SPLIT response?
Split/Retry: Can a slave use both SPLIT and RETRY responses?
Split/Retry: Do all masters have to support SPLIT and RETRY?
Split/Retry: Do all slaves have to support the SPLIT and RETRY responses?
Split/Retry: What address should be on the bus during the IDLE cycle after a SPLIT or RETRY?
Split/Retry: What is the difference between SPLIT and RETRY responses?
Split/Retry: What value should be used for HTRANS when an AHB master gets a RETRY response from a slave in the middle of burst?
Split/Retry: Will a master always lose the bus after a SPLIT response?
When should a master assert and deassert the HLOCK signal for a locked transfer?
When should a master deassert its HBUSREQ signal?
When will the arbiter grant another master after a locked transfer?
Why is there a 1KB restriction in AHB?
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