Processor Cores Knowledge Articles

Sub-Sections

• ARM10 processors
• ARM11 processors
• ARM7 processors
• ARM9 processors
• Cortex processors
• Debug and Trace

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Knowledge Articles in this section

• Are there updates to older versions of TRMs or TRM Errata Lists?
• Can I preload Tightly Coupled Memories (TCMs)?
• Can I preload caches and registers with data?
• Can I save the state of a simulation containing a DSM and restart it from the saved state?
• Can I simulate my DSMs under RedHat Enterprise Linux 3.0?
• Can I use my DSM on my 64-bit machine?
• Does my ARM DSM model work with Questasim?
• Does the DSM model the test scan chains?
• How accurate is the DSM?
• How can I check that I've installed the DSM properly?
• How do DSMs handle 'x' values in simulations?
• How do I choose ARM based processors?
• How do I get the EIS traces from multiple ARM cores in to different files?
• How do I set the cache size on my DSM?
• How do the synchronization primitives work in coherent regions of an MPCore processor
• How should cache maintenance operations be handled in systems with multi-level cache, with reference to DMA?
• I want to buy an ARM chip
• My 64 bit DSM does not work ?
• We've just received a new DSM: do I need to make any changes to my simulation environment to use it?
• What are errata 458693 and 460075 ?
• What does DSM stand for?
• What is EIS?
• What is ModelGen?
• What is SWIFT?
• What is iRM?
• Which ARM cores support the embedded Configurable Operating System (eCoS)?
• Which architectures support the WFI instruction?
• Why does the DSM CPSR contain X values after changing nIRQ/nFIQ inputs?