Embedded Trace Macrocell Architecture SpecificationETMv1.0 to ETMv3.4
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Embedded Trace Macrocell™ Architecture Specification

ETMv1.0 to ETMv3.4

Copyright © 1999-2002, 2004-2007 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Further reading
Feedback
Feedback on the Embedded Trace Macrocell
Feedback on this specification
1. Introduction
1.1. About Embedded Trace Macrocells
1.1.1. Structure of an ETM
1.1.2. The debug environment
1.1.3. Thumb and Java support
1.1.4. Trace compression
1.2. ETM versions and variants
2. Controlling Tracing
2.1. About controlling tracing
2.2. ETM event resources
2.2.1. Memory access resources
2.2.2. Instrumentation resources, ETMv3.3 and later
2.2.3. Derived resources
2.2.4. External inputs
2.2.5. Example resource configuration
2.3. ETM event logic
2.4. Triggering a trace run
2.5. External outputs
2.6. Trace filtering
2.6.1. Definitions of when an ETM is tracing
2.6.2. Behavior while tracing is prohibited
2.6.3. Programming strategies
2.6.4. TraceEnable and filtering the instruction trace
2.6.5. ViewData and filtering the data trace
2.6.6. Preventing FIFO overflow
2.7. Address comparators
2.7.1. Comparator access size
2.7.2. Comparator access size field behavior, in ETMv3.1 and later
2.7.3. Comparator access size field behavior, in ETMv3.0 and earlier
2.7.4. Exact matching, ETMv2.0 and later
2.7.5. Exact matching, ETMv1.x
2.7.6. Behavior of address comparators
2.7.7. Access types for address range comparators
2.7.8. Comparator precision
2.7.9. Coprocessor transfers
2.7.10. Comparator configuration example
2.8. Operation of data value comparators
2.8.1. Terms used in this section
2.8.2. Operation of data value comparators, ETMv3.2 and earlier
2.8.3. Operation of data value comparators, ETMv3.3 and later
2.8.4. Summary of alignment and endianness considerations for different ETM versions
2.9. Instrumentation resources, from ETMv3.3
2.9.1. The Instrumentation resource event resources
2.9.2. Instructions for controlling the Instrumentation resources
2.9.3. Instrumentation resource behavior when tracing parallel execution
2.10. Trace port clocking modes
2.10.1. ETMv1 and ETMv2 behavior
2.10.2. ETMv3 behavior
2.11. Considerations for advanced cores, ETMv2 and later only
2.11.1. Parallel execution
2.11.2. Independent load/store unit
2.11.3. Consequences of parallel execution on counters
2.11.4. Consequences of parallel execution on the sequencer
2.12. Supported standard configurations in ETMv1
2.12.1. Choosing a configuration
2.12.2. ETM7 supported configurations
2.12.3. ETM9 supported configurations
2.13. Supported configurations from ETMv2
2.14. Behavior when non-invasive debug is disabled
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Programming and reading ETM registers
3.2.1. JTAG access
3.2.2. Coprocessor access, ETMv3.1 and later
3.2.3. Memory-mapped access, ETMv3.2 and later
3.2.4. Restrictions on the type of access to ETM registers
3.2.5. ETM register access models
3.2.6. Synchronization of ETM register updates
3.3. CoreSight support
3.3.1. Programmer’s model requirements
3.3.2. Topology detection requirements
3.4. The ETM registers
3.4.1. ETM Trace and ETM Management registers, from ETMv3.3
3.4.2. Reset behavior
3.4.3. Use of the Programming bit
3.4.4. ETM Programming bit and associated state
3.5. Detailed register descriptions
3.5.1. ETM Control Register
3.5.2. ETM Configuration Code Register
3.5.3. Trigger Event Register
3.5.4. ASIC Control Register
3.5.5. ETM Status Register, ETMv1.1 and later
3.5.6. System Configuration Register, ETMv1.2 and later
3.5.7. TraceEnable registers
3.5.8. FIFO overflow registers (FIFOFULL control)
3.5.9. ViewData registers
3.5.10. Address comparator registers
3.5.11. Data value comparator registers
3.5.12. Counter registers
3.5.13. Sequencer registers
3.5.14. External Output Event Registers
3.5.15. Context ID comparator registers, ETMv2.0 and later
3.5.16. implementation specific registers
3.5.17. Synchronization Frequency Register, ETMv2.0 and later
3.5.18. ETM ID Register, ETMv2.0 and later
3.5.19. Configuration Code Extension Register, ETMv3.1 and later
3.5.20. Extended External Input Selection Register, ETMv3.1 and later
3.5.21. Trace Start/Stop EmbeddedICE Control Register, ETMv3.4 and later
3.5.22. EmbeddedICE Behavior Control Register, ETMv3.4 and later
3.5.23. CoreSight Trace ID Register, ETMv3.2 and later
3.5.24. Operating System Save and Restore Registers, ETMv3.3 and later
3.5.25. Device Power-Down Status Register (PDSR)
3.5.26. Integration Mode Control Register (ITCTRL), ETMv3.2 and later
3.5.27. Claim tag registers, ETMv3.2 and later
3.5.28. Lock registers, ETMv3.2 and later
3.5.29. Authentication Status Register (AUTHSTATUS), ETMv3.2 and later
3.5.30. Device Configuration Register (DEVID), ETMv3.2 and later
3.5.31. Device Type Register (DEVTYPE), ETMv3.2 and later
3.5.32. Peripheral identification registers, ETMv3.2 and later
3.5.33. Component identification registers, ETMv3.2 and later
3.6. Using ETM event resources
3.6.1. Resource identification
3.6.2. Boolean combinations for defining events
3.6.3. Examples of event and resource programming
3.7. Example ViewData and TraceEnable configurations
3.7.1. An example ViewData configuration
3.7.2. An example TraceEnable configuration
3.8. Power-down support, ETMv3.3 and later
3.8.1. The process of saving and restoring the macrocell ETM state
3.8.2. ETM behavior when the OS Lock is set
3.8.3. Guidelines for the ETM trace registers to be saved and restored
3.9. Access permissions for ETM registers
3.9.1. Access types
3.9.2. Meanings of terms and abbreviations used in this section
3.9.3. Restrictions on accesses using a direct JTAG connection
3.9.4. Access permissions for memory-mapped accesses
3.9.5. Access permissions for coprocessor accesses
4. Signal Protocol Overview
4.1. About trace information
4.2. Signal protocol variants
4.3. Structure of the trace port
4.3.1. Signals
4.3.2. Multiplexed trace port (ETMv1.x and ETMv2.x only)
4.3.3. Demultiplexed trace port (ETMv1.x and ETMv2.x only)
4.3.4. ETM structures
4.4. Decoding required by trace capture devices
4.4.1. Trigger conditions
4.4.2. Trace disabled conditions
4.5. Instruction trace
4.5.1. Instruction trace filtering
4.5.2. Direct and indirect branches
4.5.3. Exceptions
4.5.4. 32-bit Thumb instructions
4.5.5. Thumb CBZ and CBNZ instructions
4.6. Data trace
4.6.1. Data access filtering
4.6.2. Address and data selection
4.6.3. Preloads
4.6.4. Asynchronous data aborts
4.7. Context ID tracing
4.8. Debug state
4.9. Endian effects and unaligned access
4.9.1. Summary of ARM behavior
4.9.2. Representation of data in the trace
4.10. Definitions
4.10.1. Load/Store Multiple (LSM) instructions
4.10.2. Data Instructions
4.10.3. Direct branch instructions
4.11. Coprocessor operations
4.11.1. Coprocessor data operation
4.11.2. Coprocessor data transfer
4.11.3. Coprocessor register transfer
4.12. Wait For Interrupt and Wait For Event
5. ETMv1 Signal Protocol
5.1. ETMv1 pipeline status signals
5.1.1. Trigger PIPESTAT signals
5.2. ETMv1 trace packets
5.3. Rules for generating and analyzing the trace in ETMv1
5.3.1. Additional considerations for 16-bit ports
5.3.2. Example ETMv1 trace
5.4. Pipeline status and trace packet association in ETMv1
5.5. Instruction tracing in ETMv1
5.5.1. Direct branches to the exception vector table
5.5.2. ARM and Thumb code
5.5.3. Java code
5.5.4. Compressed branch address packet structure
5.5.5. Branch reason codes
5.6. Trace synchronization in ETMv1
5.6.1. Address Packet Offset
5.6.2. Full address output
5.6.3. Context ID tracing
5.7. Data tracing in ETMv1
5.7.1. PIPESTAT signals indicating data accesses in the pipeline
5.7.2. Load/Store Multiple instructions
5.7.3. Trace packet sequence for data accesses
5.7.4. Data aborts
5.7.5. Address compression performed by the ETM
5.8. Filtering the ETMv1 trace
5.8.1. Enabling trace
5.8.2. Disabling trace
5.8.3. Data accesses during disabled trace
5.8.4. Precise events
5.9. FIFO overflow
5.9.1. System stalling
5.10. Cycle-accurate tracing
5.11. Tracing Java code, ETMv1.3 only
6. ETMv2 Signal Protocol
6.1. ETMv2 pipeline status signals
6.1.1. Wait PIPESTAT signals
6.1.2. Branch phantom PIPESTAT signals
6.1.3. Data PIPESTAT signals
6.1.4. Instruction Executed PIPESTAT signals
6.1.5. Instruction Not Executed PIPESTAT signals
6.1.6. TD PIPESTAT signals
6.1.7. Trigger PIPESTAT signals
6.2. ETMv2 trace packets
6.3. Rules for generating and analyzing the trace in ETMv2
6.4. Trace packet types
6.4.1. Trace packet headers
6.4.2. Normal Data packets
6.4.3. Load Miss packets
6.4.4. Value Not Traced packets
6.4.5. Context ID packets
6.5. Trace synchronization in ETMv2
6.5.1. Trace FIFO offsets
6.5.2. TFO packet types
6.5.3. TFO packet headers
6.5.4. Normal TFO packets
6.5.5. LSM In Progress TFO packets
6.5.6. Data address synchronization
6.5.7. Context ID tracing
6.6. Tracing through regions with no code image
6.7. Instruction tracing with ETMv2
6.7.1. Branch Address trace packets
6.7.2. Full branch address reason codes
6.8. Data tracing in ETMv2
6.8.1. Data aborts
6.8.2. Decoding the data trace packets
6.8.3. Address compression performed by the ETM
6.9. Filtering the ETMv2 trace
6.9.1. Enabling trace
6.9.2. Disabling trace
6.9.3. Data accesses during disabled trace
6.10. FIFO overflow
6.11. Cycle-accurate tracing
7. ETMv3 Signal Protocol
7.1. Introduction
7.2. Packet types
7.3. Instruction tracing
7.3.1. P-headers
7.3.2. Condition codes on canceled and undefined instructions
7.3.3. Cycle information, for cycle-accurate tracing
7.3.4. Cycle count packet
7.3.5. Branch packets
7.3.6. Context ID packets
7.4. Data tracing
7.4.1. Data packet types
7.4.2. Normal data packet
7.4.3. Out-of-order packets
7.4.4. Tracing LSMs
7.4.5. Value not traced packet
7.4.6. Data suppressed packet
7.4.7. Store failed packet
7.4.8. Jazelle data tracing
7.4.9. Data aborts
7.4.10. Data-only mode, ETMv3.1 and later
7.4.11. Data tracing options, ETMv3.3 and later
7.4.12. Exceptions on Data Instructions
7.5. Additional trace features for ARMv7‑M cores, from ETMv3.4
7.5.1. Support for a large number of exceptions
7.5.2. Instructions that can be paused for continuation
7.5.3. Automatic stack push on exception entry and pop on exception exit
7.5.4. Tracing return from an exception
7.6. Behavior of EmbeddedICE inputs, from ETMv3.4
7.6.1. EmbeddedICE watchpoint comparator input behavior
7.6.2. Default behavior of EmbeddedICE watchpoint inputs
7.6.3. Implementation of pulse and latch behavior of EmbeddedICE inputs
7.6.4. EmbeddedICE input usage examples
7.7. Synchronization
7.7.1. Frequency of synchronization
7.7.2. A-sync, alignment synchronization
7.7.3. I-sync instruction synchronization
7.7.4. D-sync, data address synchronization
7.8. Trace port interface
7.8.1. Trigger
7.8.2. Ignore
7.8.3. FIFO draining
7.9. Tracing through regions with no code image
7.10. Cycle-accurate tracing
7.10.1. Tracing long gaps in cycle-accurate trace
7.10.2. Support for cycle-accurate tracing, ETMv3.3 and later
7.11. ETMv2 and ETMv3 compared
7.11.1. ETMv2 PIPESTAT encodings and ETMv3 P-headers compared
7.11.2. ETMv2 TFO packets and ETMv3 I-sync packets compared
8. Trace Port Physical Interface
8.1. Target system connector
8.2. Target connector pinouts
8.2.1. Assignment of trace information pins between ETM architecture versions
8.2.2. Single target connector pinout
8.2.3. Dual target connector pinout
8.2.4. Multiplexed trace port, single target connector pinout (ETMv1.x and ETMv2.x)
8.2.5. Demultiplexed trace port target connector pinout
8.2.6. Signal descriptions
8.3. Connector placement
8.3.1. Connector orientation
8.3.2. Dual connector placement
8.4. Timing specifications
8.4.1. Half-rate clocking mode
8.5. Signal level specifications
8.6. Other target requirements
8.7. JTAG control connector
9. Tracing Dynamically Loaded Images
9.1. About tracing dynamically-loaded code
9.1.1. Simple overlay support
9.2. Software support for Context ID
9.3. Hardware support for Context ID
A. ETM Quick Reference information
A.1. ETM Event Resources
A.1.1. Resource identification and event encoding
A.1.2. Resource control registers
A.2. Summary of branch packets, ETMv3.0 and later
A.3. Summary of implementation defined ETM features
B. Architecture Version Information
B.1. ETMv1
B.1.1. ETMv1.0 to ETMv1.1
B.1.2. ETMv1.1 to ETMv1.2
B.1.3. ETMv1.2 to ETMv1.3
B.2. ETMv2
B.2.1. ETMv1.3 to ETMv2.0
B.2.2. ETMv2.0 to ETMv2.1
B.3. ETMv3
B.3.1. ETMv2.1 to ETMv3.0
B.3.2. ETMv3.0 to ETMv3.1
B.3.3. ETMv3.1 to ETMv3.2
B.3.4. ETMv3.2 to ETMv3.3
B.3.5. ETMv3.3 to ETMv3.4
Glossary

List of Figures

1.1. Example debugging environment with TPA
1.2. Example debugging environment with ETB
2.1. Sequencer state diagram
2.2. Extended external inputs example
2.3. Example resource configuration
2.4. TraceEnable configuration
2.5. Programming the TraceEnable logic
2.6. Trace start/stop block
2.7. ViewData configuration
2.8. Programming the ViewData logic
2.9. FIFOFULL generation
2.10. Programming the FIFOFULL logic
2.11. SuppressData inputs
2.12. Programming the data suppression logic
2.13. Single address comparisons in ETMv3.1 and later
2.14. Range comparisons in ETMv3.1 and later
2.15. Successful match of a byte access with word mask set
2.16. Successful match of word access with word mask set
2.17. Successful match of byte access on byte watch with word mask set
2.18. Unwanted match of byte access on byte watch with word mask set
2.19. Failed match with no mask
2.20. Range address successful match, ETMv3.0 or earlier
2.21. Range address failed match, ETMv3.0 or earlier
3.1. ETM JTAG structure
3.2. Mapping from register number to CP14 instruction fields
3.3. Programming ETM registers
3.4. ETM Control Register bit assignments for architecture v3.3
3.5. ETM Configuration Code Register bit assignments, from architecture v3.1
3.6. ETM Configuration Code Register bit assignments for architecture v1.x
3.7. Trigger Event Register bit assignments
3.8. ASIC Control Register bit assignments
3.9. ETM Status Register bit assignments for architecture v3.1
3.10. System Configuration Register bit assignments for architecture v3.2
3.11. Trace Start/Stop Resource Control Register bit assignments
3.12. TraceEnable Control 2 Register bit assignments
3.13. TraceEnable Control 1 Register bit assignments
3.14. TraceEnable Event Register bit assignments
3.15. FIFOFULL Region Register bit assignments
3.16. FIFOFULL Level Register bit assignments
3.17. ViewData Event Register bit assignments
3.18. ViewData Control 1 Register bit assignments
3.19. ViewData Control 2 Register bit assignments
3.20. ViewData Control 3 Register bit assignments
3.21. Address Comparator Value Registers, bit assignments
3.22. Address Access Type Registers, bit assignments
3.23. Data Comparator Value Registers, bit assignments
3.24. Data Comparator Mask Registers, bit assignments
3.25. Counter Reload Value Registers, bit assignments
3.26. Counter Enable Registers, bit assignments
3.27. Counter Reload Event Registers, bit assignments
3.28. Counter Value Registers, bit assignments
3.29. Sequencer State Transition Event Registers, bit assignments
3.30. Current Sequencer State Register bit assignments
3.31. External Output Event Registers, bit assignments
3.32. Context ID Comparator Value Registers, bit assignments
3.33. Context ID Comparator Mask Register bit assignments
3.34. implementation specific Register 0 bit assignments
3.35. Synchronization Frequency Register bit assignments
3.36. ETM ID Register bit assignments, for ETM architecture v3.4
3.37. Configuration Code Extension Register bit assignments, ETMv3.4 and later
3.38. Extended External Input Selection Register bit assignments
3.39. Trace Start/Stop EmbeddedICE Control Register bit assignments
3.40. EmbeddedICE Behavior Control Register bit assignments
3.41. CoreSight Trace ID Register bit assignments
3.42. OS Lock Access Register (OSLAR) bit assignments
3.43. OS Lock Status Register (OSLSR) bit assignments
3.44. OS Save and Restore Register (OSSRR) bit assignments
3.45. PDSR bit assignments
3.46. Integration Mode Control Register bit assignments
3.47. Claim Tag Set Register bit assignments
3.48. Claim Tag Clear Register bit assignments
3.49. Lock Access Register bit assignments
3.50. Lock Status Register bit assignments
3.51. Authentication Status Register bit assignments
3.52. Secure non-invasive debug enable logic when controlled by the ETM
3.53. Device Configuration Register bit assignments
3.54. Device Type Register bit assignments
3.55. Mapping between the Peripheral ID Registers and the Peripheral ID value
3.56. Peripheral ID fields
3.57. Peripheral ID0 Register bit assignments
3.58. Peripheral ID1 Register bit assignments
3.59. Peripheral ID2 Register bit assignments
3.60. Peripheral ID3 Register bit assignments
3.61. Peripheral ID4 Register bit assignments
3.62. Peripheral ID5 to Peripheral ID7 Registers, bit assignments
3.63. Mapping between the Component ID Registers and the Component ID value
3.64. Component ID0 Register bit assignments
3.65. Component ID1 Register bit assignments
3.66. Component ID2 Register bit assignments
3.67. Component ID3 Register bit assignments
3.68. Event and resource encoding
3.69. Example ViewData configuration
3.70. ViewData Event Register example
3.71. ViewData Control 1 Register example
3.72. ViewData Control 3 Register example
3.73. Example ViewData composite range
3.74. Example TraceEnable configuration
3.75. TraceEnable Event Register example
3.76. TraceEnable Control 1 Register example
3.77. Trace Start/Stop Resource Control Register example
4.1. ETMv1.x structure
4.2. ETMv2.x structure
4.3. ETMv3.x structure
5.1. Full address output in ARM and Thumb state
6.1. Generating an ARM branch address
6.2. Generating a Thumb branch address
6.3. Full branch address encodings for ARM and Thumb states
7.1. Cycle count packet
7.2. Branch packet to an instruction in ARM state
7.3. Branch packet to an instruction in Thumb state
7.4. Branch packet to instruction in Jazelle state
7.5. Branch packet to an exception vector in ARM state (5-byte packet)
7.6. Branch packet to an exception vector in ARM state, with Exception information byte
7.7. Normal Thumb branch with no change in address bits [31:7]
7.8. Normal Thumb branch with no change in address bits [31:14]
7.9. Normal Thumb branch with no change in address bits [31:21]
7.10. Normal Thumb branch with no change in address bits [31:28]
7.11. Normal Thumb branch with a change in address bits [31:28]
7.12. Alternative encoding of normal Thumb branch with no change in address bits [31:7]
7.13. Alternative encoding of normal Thumb branch with no change in address bits [31:13]
7.14. Alternative encoding of normal Thumb branch with no change in address bits [31:20]
7.15. Alternative encoding of normal Thumb branch with no change in address bits [31:27]
7.16. Alternative encoding of normal Thumb branch when address bits [31:27] change
7.17. Alternative encoding of normal ARM branch with no change in address bits [31:14]
7.18. Alternative encoding of normal Jazelle branch with no change in address bits [31:19]
7.19. Exception Thumb branch with no change in address bits [31:13], alternative encoding
7.20. Exception Thumb branch with no change in address bits [31:20], alternative encoding
7.21. Exception Thumb branch with no change in address bits [31:27], alternative encoding
7.22. Exception Thumb branch when address bits [31:27] change, alternative encoding
7.23. Exception ARM branch with no change in address bits [31:21], alternative encoding
7.24. Exception Jazelle branch with no change in address bits [31:26], alternative encoding
7.25. Extended exception branch packet, shown for Thumb state
7.26. Only Exception information byte 0 is output
7.27. Only Exception information bytes 0 and 1 are output
7.28. Only Exception information bytes 0 and 2 are output
7.29. All Exception information bytes are output
7.30. Generating an ARM branch address
7.31. Generating a Thumb branch address
7.32. Generating a Jazelle branch address
7.33. Context ID packet
7.34. Normal data packet for ETMv3.0 and later
7.35. Out-of-order placeholder packet
7.36. Out-of-order data packet for ETMv3.0 and later
7.37. Value not traced packet
7.38. Data suppressed packet
7.39. Store failed packet
7.40. Exception entry packet, ETMv3.4 and later
7.41. Return from exception packet, ETMv3.4 and later
7.42. Normal I-sync packet
7.43. Normal I-sync with cycle count packet
7.44. LSiP I-sync packet
7.45. LSiP I-sync with cycle count packet
7.46. Data-only I-sync packet
7.47. Trigger packet
7.48. Ignore packet
8.1. Recommended connector orientation
8.2. Recommended dual connector orientation
8.3. TRACECLK specification
8.4. Trace data specification
9.1. SDRAM overlay examples
9.2. Memory map and overlay physical address space
A.1. Writing to an Event Register

List of Tables

1.1. ETM versions and variants
2.1. Filter CPRT and monitor CPRT combinations
2.2. Testing whether data suppression is supported, ETMv3.3 and later
2.3. Permitted Suppress data and Stall processor settings, ETM Control Register
2.4. Effect of exact match bit settings for instruction address comparisons
2.5. Data value comparisons for normal transfers
2.6. Data value comparisons on an out-of-order transfer
2.7. Context-dependent behavior of single address comparators
2.8. Context-dependent behavior of address range comparators, from ETMv3.3
2.9. Context-dependent behavior of address range comparators, before ETMv3.3
2.10. Single address and address range comparators example
2.11. Alignment considerations in ETMv1.x
2.12. Alignment considerations in ETMv2.0 to ETMv3.2
2.13. Alignment considerations in ETMv3.3 and later
2.14. The instrumentation resource event resources
2.15. Hint field encodings for the instrumentation instructions
2.16. Instrumentation resource parallel execution examples, for two instructions
2.17. Clocking, port mode, port speed, and data pins in ETMv1 and ETMv2
2.18. Port mode, port speed and data pins in ETMv3
2.19. ETM7 configurations
2.20. ETM9 configurations
3.1. Typical ETM register access implementations
3.2. ETM logical interfaces
3.3. ETM registers summary
3.4. Split of ETM register map into Trace and Management registers
3.5. ETM Control Register bit assignments
3.6. ETM port size
3.7. ETM Control Register checks for implementation defined features
3.8. Testing whether cycle-accurate tracing is supported, ETMv3.3 and later
3.9. Testing which data tracing features are implemented, ETMv3.3 and later
3.10. ETM Configuration Code Register bit assignments
3.11. Trigger Event Register bit assignments
3.12. ASIC Control Register bit assignments
3.13. ETM Status Register bit assignments
3.14. System Configuration Register bit assignments
3.15. Trace Start/Stop Resource Control Register bit assignments
3.16. TraceEnable Control 2 Register bit assignments
3.17. TraceEnable Control 1 Register bit assignments
3.18. TraceEnable Event Register bit assignments
3.19. FIFOFULL Region Register bit assignments
3.20. FIFOFULL Level Register bit assignments
3.21. Supported FIFOFULL and data suppression modes in ETMv3.0 and later
3.22. ViewData Event Register bit assignments
3.23. ViewData Control 1 Register bit assignments
3.24. ViewData Control 2 Register bit assignments
3.25. ViewData Control 3 Register bit assignments
3.26. Address Comparator Value Registers, bit assignments
3.27. Address Access Type Registers, bit assignments
3.28. Summary of the data value comparator registers
3.29. Data Comparator Value Registers, bit assignments
3.30. Data Comparator Mask Registers, bit assignments
3.31. Example comparator register associations for a medium-sized configuration
3.32. Summary of Counter registers
3.33. Counter Reload Value Registers, bit assignments
3.34. Counter Enable Registers, bit assignments
3.35. Counter Reload Event Registers, bit assignments
3.36. Counter Value Registers, bit assignments
3.37. Sequencer register allocation
3.38. Sequencer State Transition Event Registers, bit assignments
3.39. Current Sequencer State Register bit assignments
3.40. External Output Event Registers, bit assignments
3.41. Summary of the Context ID comparator registers
3.42. Context ID Comparator Value Registers, bit assignments
3.43. Context ID Comparator Mask Register bit assignments
3.44. implementation specific Register 0 bit assignments
3.45. Synchronization Frequency Register bit assignments
3.46. ETM ID Register bit assignments
3.47. ID values for different ETM variants
3.48. Configuration Code Extension Register bit assignments
3.49. Extended External Input Selection Register bit assignments
3.50. Trace Start/Stop EmbeddedICE Control Register bit assignments
3.51. EmbeddedICE Behavior Control Register bit assignments
3.52. CoreSight Trace ID Register bit assignments
3.53. OS Lock Access Register (OSLAR) bit assignments
3.54. OS Lock Status Register (OSLSR) bit assignments
3.55. OS Save and Restore Register (OSSRR) bit assignments
3.56. PDSR bit assignments
3.57. PDSR encodings
3.58. Integration Mode Control Register bit assignments
3.59. Claim Tag Set Register bit assignments
3.60. Claim Tag Clear Register bit assignments
3.61. Lock Access Register bit assignments
3.62. Lock Status Register bit assignments
3.63. Authentication Status Register bit assignments
3.64. Implementation of the Secure non-invasive debug field
3.65. Device Configuration Register bit assignments
3.66. Device Type Register bit assignments
3.67. Summary of the peripheral identification registers
3.68. Register fields for the peripheral identification registers
3.69. Peripheral ID0 Register bit assignments
3.70. Peripheral ID1 Register bit assignments
3.71. Peripheral ID2 Register bit assignments
3.72. Peripheral ID3 Register bit assignments
3.73. Peripheral ID4 Register bit assignments
3.74. Peripheral ID5 to Peripheral ID7 Registers, bit assignments
3.75. Summary of the component identification registers
3.76. Component ID0 Register bit assignments
3.77. Component ID1 Register bit assignments
3.78. Component ID2 Register bit assignments
3.79. Component ID3 Register bit assignments
3.80. Resource encodings
3.81. Resource identification encoding
3.82. Boolean function encoding for events
3.83. Event encoding
3.84. Example comparator inputs
3.85. TraceEnable Control 1 Register example values
3.86. Split of ETM register map into Trace and Management registers
3.87. Typical list of ETM registers to be saved and restored
3.88. Debugger accesses to ETM memory-mapped registers, except the OS Save and Restore registers, separate debug and core power domains 
3.89. Debugger accesses to ETM memory-mapped OS Save and Restore registers, separate debug and core power domains 
3.90. Software accesses to ETM memory-mapped registers, except the OS Save and Restore registers, separate debug and core power domains 
3.91. Software accesses to ETM memory-mapped OS Save and Restore registers, separate debug and core power domains 
3.92. Debugger accesses to ETM memory-mapped registers, except the OS Save and Restore registers, for SinglePower system 
3.93. Debugger accesses to ETM memory-mapped OS Save and Restore registers, for SinglePower system 
3.94. Software accesses to ETM memory-mapped registers, except the OS Save and Restore registers, for SinglePower system 
3.95. Software accesses to ETM memory-mapped OS Save and Restore registers, for SinglePower system 
3.96. Coprocessor accesses to ETM registers, separate debug and core power domains 
3.97. Coprocessor accesses to ETM registers, for SinglePower system 
4.1. Trace disabled conditions
4.2. ETMv3 exception tracing
4.3. ETM Control Register ProcIDSize bits
5.1. PIPESTAT messages
5.2. PIPESTAT and TRACEPKT association
5.3. Branch reason codes
6.1. PIPESTAT messages
6.2. Trace packet header encodings
6.3. SS bit encodings
6.4. TFO encodings
6.5. Example signal sequence for a mid-byte TFO
6.6. TFO packet header encodings
6.7. TFO reason codes
6.8. Comparison of Normal and LSM in progress TFO packets
6.9. ARM and Thumb 5-byte addresses
7.1. Header encodings
7.2. P-header encodings in non cycle-accurate mode
7.3. Cycle count and P-header encodings in cycle-accurate mode
7.4. Use of format 4 P-header in cycle-accurate mode
7.5. Summary of branch packet lengths, with original and alternative address compression
7.6. Interpretation of bits [7:6], alternative branch compression encoding
7.7. Meaning of bits [7:6] of byte five of a branch packet on the original address compression scheme
7.8. Encoding of byte five of Branch address packets on the original address compression scheme
7.9. Exception encodings for bits [5:3] of the fifth address byte
7.10. Exception information byte 0 encoding
7.11. Meaning of the AltISA bit in the Continuation byte
7.12. Encoding of Exception[3:0] for non-ARMv7-M cores
7.13. Handling of missing Branch address packet components
7.14. State change packets
7.15. Direct branch with change from ARM to Thumb state
7.16. Direct branch with changes between Thumb and ThumbEE states
7.17. Encoding of Exception[8:0] for ARMv7-M processors
7.18. Encoding of the Can bit and Resume[3:0]
7.19. Size bit encoding combinations
7.20. Possible feature sets for data tracing, ETMv3.3 and later
7.21. Default behavior of EmbeddedICE watchpoint comparator inputs
7.22. Processor state information in I-sync packets, ETMv3.3 and later
7.23. ETMv3 reason codes
7.24. Mappings from pipeline status to P-header atoms
8.1. Connector part numbers
8.2. Trace signal names
8.3. Single target connector pinout
8.4. Pipeline status seen by old TPAs
8.5. Second target connector pinout ETMv3.x
8.6. Dual target connector pinout
8.7. Multiplexed trace port, single target connector pinout
8.8. Paired signals in a multiplexed trace port connector
8.9. Demultiplexed 4-bit connector pinout
8.10. TRACECLK timing requirements
8.11. Rise and fall time requirements
8.12. Trace port setup and hold requirements
A.1. Resource identification encoding
A.2. Boolean function encoding for events
A.3. Locations of ETM event registers
A.4. ASIC Control Register, 0x003
A.5. Trace Start/Stop Resource Control Register, 0x006
A.6. TraceEnable Control 1 Register, 0x009
A.7. TraceEnable Control 2 Register, 0x007
A.8. FIFOFULL Region Register, 0x00A
A.9. FIFOFULL Level Register, 0x00B
A.10. ViewData Control 1 Register, 0x00D
A.11. ViewData Control 2 Register, 0x00E
A.12. ViewData Control 3 Register, 0xo0F
A.13. Address Comparator Value Registers, 0x010-0x01F
A.14. Address Access Type Registers, 0x020-0x02F
A.15. Exact match bit settings for instruction accesses
A.16. Exact match bit settings for data accesses
A.17. Data Comparator Value Registers, 0x030-0x03F
A.18. Data Comparator Mask Registers, 0x040-0x04F
A.19. Counter Reload Value Registers, 0x050-0x053
A.20. Counter Enable Registers, 0x054-0x057
A.21. Counter Value Registers, 0x05C-0x05F
A.22. Current Sequencer State Register, 0x067
A.23. External Output Event Registers, 0x068-0x06B
A.24. Locations of the Context ID Comparator Value Registers
A.25. Context ID Comparator Value Registers, 0x06C-0x06E
A.26. Context ID Comparator Mask Register, 0x06F
A.27. Synchronization Frequency Register, 0x078
A.28. Extended External Input Selection Register, 0x07B
A.29. Full list of branch packets with content summary, ETMv3.0 and later
A.30. ETMv3.4 features with implementation defined number of instances or size
A.31. Optional features in ETMv3.4

Proprietary Notice

ARM, the ARM Powered logo, Jazelle, RealView and Thumb are registered trademarks of ARM Limited.

The ARM logo, AMBA, ARM7TDMI, ARM7TDMI-S, CoreSight, Cortex, EmbeddedICE, ETM, ETM7, ETM9, and TDMI, are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarks of their respective owners.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith.

1. Subject to the provisions set out below, ARM hereby grants to you a perpetual, non-exclusive, nontransferable, royalty free, worldwide licence to use this ARM Embedded Trace Macrocell Architecture Specification for the purposes of developing; (i) software applications or operating systems which are targeted to run on microprocessor cores distributed under licence from ARM; (ii) tools which are designed to develop software programs which are targeted to run on microprocessor cores distributed under licence from ARM; (iii) integrated circuits which incorporate a microprocessor core manufactured under licence from ARM.

2. Except as expressly licensed in Clause 1 you acquire no right, title or interest in the ARM Embedded Trace Macrocell Architecture Specification, or any Intellectual Property therein. In no event shall the licences granted in Clause 1, be construed as granting you expressly or by implication, estoppel or otherwise, licences to any ARM technology other than the ARM Embedded Trace Macrocell Architecture Specification. The licence grant in Clause 1 expressly excludes any rights for you to use or take into use any ARM patents. No right is granted to you under the provisions of Clause 1 to; (i) use the ARM Embedded Trace Macrocell Architecture Specification for the purposes of developing or having developed microprocessor cores or models thereof which are compatible in whole or part with either or both the instructions or programmer's models described in this ARM Embedded Trace Macrocell Architecture Specification; or (ii) develop or have developed models of any microprocessor cores designed by or for ARM; or (iii) distribute in whole or in part this ARM Embedded Trace Macrocell Architecture Specification to third parties without the express written permission of ARM; or (iv) translate or have translated this ARM Embedded Trace Macrocell Architecture Specification into any other languages.

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Revision History
Revision A30 March 1999First release for ETMv1.0 and ETMv1.1.
Revision B12 July 1999Errata 01 corrections incorporated for ETMv1.1 and ETMv1.0.
Revision C03 December 1999Protocol enhancements and modified trace port connector pinout added. ETMv1.0 and ETMv1.1 release.
Revision D18 May 2000Protocol version 2 enhancements added. ETMv1.2 release.
Revision E06 September 2000Minor corrections to Issue D incorporated. ETMv1.2 release.
Revision F15 January 2001Protocol version 3 enhancements added to support the tracing of Java instructions. ETMv1.3 release.
Revision G08 May 2001Description of protocol versions and variants included. Released in conjunction with fixes to errata in ETMv1.2 and ETMv1.3.
Revision H25 July 2001Description of ETMv2.0 enhancements included.
Revision I17 December 2002Incorporation of ETMv2.1, ETMv3.0, and ETMv3.1 architectures.
Revision J16 July 2004Incorporation of ETMv3.2 architecture.
Revision K17 March 2005Minor corrections and updates.
Revision L04 November 2005Incorporates ETMv3.3 architecture, re-organizes descriptions of address comparators, and has minor enhancements elsewhere.
Revision M14 December 2005Final draft of ETMv3.4 issue.
Revision N08 February 2006Non-confidential release of ETMv3.4 issue. No change to content.
Revision O20 July 2007Various enhancements, updates and corrections, incorporating all errata to Issue N. Updated Implementer codes list. Added summary of implementation defined ETM features to Appendix A.
Copyright © 1999-2002, 2004-2007 ARM Limited. All rights reserved.ARM IHI 0014O
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