3.12.1. ETM state definitions, ETMv3.5, SinglePower

The following list shows the definitions of ETM states for SinglePower implementations in ETMv3.5. These states determine the behavior of accesses to the registers listed in the tables in this section.

No Power

This behavior applies if the ETM is powered down. Also, for memory-mapped accesses, this state applies when DBGSWENABLE is LOW.

Non-Privileged

This behavior applies to coprocessor accesses when all of the following apply:

  • the ETM is not in the No Power state

  • the processor is operating in a Non-Privileged mode

  • accesses to the ETM are disabled using the CPACR, NSACR or HCPTR.

If the ETM is in a state which is not covered by one of these definitions then the general access permissions apply as defined in the Otherwise column in each table.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211