3.13.1. ETM state definitions, ETMv3.5, multiple power domains

The following list shows the definitions of ETM states for multiple power implementations, in ETMv3.5. These states determine the behavior of accesses to the registers listed in the tables in this section.

No Debug Power

This behavior applies when the debug domain is powered down. Also, for memory-mapped accesses, this behavior applies when DBGSWENABLE is LOW.

No Core Power

The behavior applies when all of the following apply:

  • the core power domain is powered down.

  • for debugger and memory-mapped accesses, the ETM is not in the No Debug Power state

OS Lock set

The behavior applies when all of the following apply:

  • the ETM is not in the No Debug Power state

  • the ETM is not in the No Core Power state

  • the OS Lock is set to 1.

Non-Privileged

This behavior applies to coprocessor accesses when all of the following apply:

  • the ETM is not in the No Debug Power state

  • the ETM is not in the No Core Power state

  • the processor is operating in a Non-Privileged mode

  • accesses to the ETM are disabled using the CPACR, NSACR or HCPTR.

This state takes precedence over the OS Lock Set state.

If the ETM is in a state which is not covered by one of the definitions listed here then the general access permissions apply as defined in the Otherwise column in each table.

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