3.5.49. ETM ID Register 2, ETMIDR2, ETMv3.5

The ETMIDR2 characteristics are:

Purpose

Provides an extension to the ETM ID register, ETMIDR.

Usage constraints

There are no usage constraints.

Configurations

This register is only available in ETMv3.5 or later.

Attributes

See the register summary in Table 3.3 and Reset behavior.

Figure 3.45 shows the ETMIDR2 bit assignments.

Figure 3.45. ETMIDR2 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.59 shows the ETMIDR2 bit assignments.

Table 3.59. ETMIDR2 bit assignments

Bits

Version [a]

Description

[31:2]-Reserved.
[1]v3.5

Identifies the order of transfers for a SWP or SWPB instruction:

0 = the Load transfer is traced before the Store transfer

1 = the Store transfer is traced before the Load transfer

[0]v3.5

Identifies the order of transfers for the RFE instruction:

0 = the PC transfer is traced before the CPSR transfer

1 = the CPSR transfer is traced before the PC transfer

[a] The first ETM architecture version that defines the field.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211