3.11.1. ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains

The following list shows the definitions of ETM states for multiple power implementations in ETMv3.3 and ETMv3.4. These states determine the behavior of accesses to the registers listed in the tables in this section.

No Debug Power

This behavior applies if the ETM is powered down. Also, for memory-mapped accesses, this state applies when DBGSWENABLE is LOW.

No Core Power

This behavior applies when all the following apply:

  • the ETM is not in the No Debug Power state

  • the core domain is powered down.

Sticky State Set

This behavior applies when all the following apply:

  • the ETM is not in the No Debug Power state

  • the ETM is not in the No Core Power state

  • the Sticky State is set to 1.

OS Lock set

This behavior applies when all the following apply:

  • the ETM is not in the No Debug Power state

  • the ETM is not in the No Core Power state

  • the ETM is not in the Sticky State Set state

  • the OS Lock is set to 1.

Non-Privileged

This behavior applies to coprocessor accesses when all the following apply:

  • the ETM is not in the No Debug Power state

  • the ETM is not in the No Core Power state

  • the processor is operating in a Non-Privileged mode

  • accesses to the ETM are disabled using the CPACR, NSACR or HCPTR.

This state takes precedence over the Sticky State Set or OS Lock Set states.

If the ETM is in a state which is not covered by one of the definitions listed here then the general access permissions apply as defined in the Otherwise column in each table.

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