3.8.2. Power down support in ETMv3.5

Two levels of power down support are provided in ETMv3.5, SinglePower and Full support.

SinglePower in ETMv3.5

A SinglePower implementation can be identified by reading the ETMOSLSR. If bit [3] and bit [0] of the ETMOSLSR are both 0 then this is a SinglePower implementation.

SinglePower implementations do not support tracing over a power down. To avoid losing ETM state when the processor is powered down, one of the following options must be used:

  • Do not power down the processor. This can be achieved by setting the DBGNOPWRDWN bit in the processor debug registers.

  • The ETM must remain powered when the processor is powered down. This involves implementing the ETM in a separate power domain from the processor.

  • The ETM registers must be manually saved by software running on the processor. This mechanism does not guarantee that the processor and an external debugger do not conflict while the saving and restoring is taking place.

A SinglePower implementation has the following attributes:

  • The OS Lock is not implemented:

    • The ETMOSLAR is not implemented and ignores writes

    • The ETMOSSRR is not implemented and accesses to the ETMOSSRR are unpredictable

    • The ETMOSLSR always reads as 0x00000000.

  • The ETMPDSR always reads as 0x00000001.

  • The ETMPDCR is not implemented.

For more details on Access permissions in SinglePower implementations see Access permissions for ETMv3.5, SinglePower.

Full Power Down Support in ETMv3.5

An implementation with Full Power Down support can be identified by reading the ETMOSLSR. If bit [3] is 1 and bit [0] is 0 then the implementation has full power down support.

Full power down support in ETMv3.5 has the following attributes:

  • The OS Lock is implemented:

    • The OS Lock is set from an ETM reset.

    • The ETMOSLAR is implemented.

    • The ETMOSSRR is not implemented. Trace registers must be manually saved and restored while the OS Lock is set.

    • When the OS Lock is set, accesses to Trace registers from an external debugger return an Error.

  • The ETMPDSR is fully implemented:

    • The StickyState bit has no effect on accesses to any registers.

  • The ETMPDCR is implemented.

For more details on Access permissions implementations with full power down support see Access permissions for ETMv3.5, multiple power domains.

To save the ETM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers, ETMv3.2 and later.

  2. Set the OS Lock using the ETMOSLAR. See About the Operating System Save and Restore Registers, ETMv3.3 and later.

  3. Poll ETMSR bit [1] until it becomes set, indicating the ETM is idle. See ETM Status Register, ETMSR, ETMv1.1 and later.

  4. Manually read the ETM trace registers and save the contents to memory.

  5. If using coprocessor instructions to access the ETM registers, the relevant bit in the CPACR might have to be set to prevent any more coprocessor accesses to the ETM registers.

  6. The ETM core domain can now be powered down.

If the procedure is terminated early, for example if the power down sequence is terminated before this procedure is complete, if the OS Lock is cleared before the ETMSR bit [1] is set then the ETM might not restart tracing immediately and the ETM resources might not become active immediately.

To restore the ETM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers, ETMv3.2 and later.

  2. If using coprocessor instructions to access the ETM registers, the relevant bit in the CPACR might have to be cleared to enable coprocessor accesses to the ETM registers.

  3. The OS Lock must be set from an ETM reset. Check this by reading the ETMOSLSR. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later.

  4. Poll the ETMSR bit [1] until it becomes set, indicating the ETM is idle. See ETM Status Register, ETMSR, ETMv1.1 and later.

  5. Manually restore the ETM trace registers from memory.

  6. Clear the OS Lock using the ETMOSLAR. See OS Lock Access Register, ETMOSLAR, ETMv3.3 and later.

Significant changes to power down support introduced in ETMv3.5

  • The ETMOSSRR is never implemented.

  • If implemented, the OS Lock is set from an ETM reset.

  • If implemented, if the OS Lock is set it only causes an error response to debugger accesses to the ETM Trace registers.

  • If implemented, the ETMPDSR bit [1], Sticky Register State, no longer has any effect on accesses to any ETM registers.

  • The OS Lock status is visible in the ETMPDSR.

  • The Claim tag registers are now ETM Trace registers and must be saved and restored manually.

  • The ETMSR bit [1] becomes set when the ETM becomes idle after setting the OS Lock. This is used to indicate that the ETM is sufficiently idle for the ETM trace registers to be saved or restored.

  • Access permissions to some registers are changed. See About the access permissions for ETM registers.

  • The ETMPDCR is implemented.

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