3.8.1. Power down support in ETMv3.3 and ETMv3.4

Two levels of power down support are provided in ETMv3.3 and ETMv3.4, SinglePower and Full support.

SinglePower in ETMv3.3 and ETMv3.4

A SinglePower implementation can be identified by reading the ETMOSLSR. If bit [3] and bit [0] of the ETMOSLSR are both 0 then this is a SinglePower implementation.

SinglePower implementations do not support tracing over a power down. To avoid losing ETM state when the processor is powered down, one of the following options must be used:

  • Do not power down the processor. This can be achieved by setting the DBGNOPWRDWN bit in the processor debug registers.

  • The ETM must remain powered when the processor is powered down. This involves implementing the ETM in a separate power domain from the processor.

  • The ETM registers must be manually saved by software running on the processor. This mechanism does not guarantee that the processor and an external debugger do not conflict while the saving and restoring is taking place.

A SinglePower implementation has the following attributes:

  • The OS Lock is not implemented:

    • The ETMOSLAR is not implemented and ignores writes

    • The ETMOSSRR is not implemented and accesses to the ETMOSSRR are Unpredictable

    • The ETMOSLSR always reads as 0x00000000

  • The ETMPDSR always reads as 0x00000001

For more details on Access permissions in SinglePower implementations see Access permissions for ETMv3.3 and ETMv3.4, SinglePower.

Full Power Down Support in ETMv3.3 and ETMv3.4

An implementation with Full Power Down support can be identified by reading the ETMOSLSR. If bit [3] is b0 and bit [0] is b1 then the implementation has full power down support.

Full power down support has the following attributes:

  • The OS Lock is implemented:

    • The ETMOSLAR is implemented

    • The ETMOSSRR is implemented and is used to save and restore the ETM trace registers

    • When the OS Lock is set, accesses to Trace registers return an Error

  • The ETMPDSR is fully implemented:

    • When the StickyState bit [1] is set, accesses to Trace registers return an Error

For more details on Access permissions implementations with full power down support see Access permissions for ETMv3.3 and ETMv3.4, multiple power domains.

To save the ETM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers, ETMv3.2 and later.

  2. Read the ETMPDSR to clear the StickyState bit if it is set. See Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later.

  3. Set the OS Lock using the ETMOSLAR. See About the Operating System Save and Restore Registers, ETMv3.3 and later.

  4. Use the ETMOSSRR to read out the ETM registers and save them to memory. See OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later.

  5. The ETM core domain can now be powered down.

To restore the ETM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers, ETMv3.2 and later.

  2. Read the ETMPDSR to clear the StickyState bit. See Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later.

  3. Set the OS Lock if it is not already set using the ETMOSLAR. See About the Operating System Save and Restore Registers, ETMv3.3 and later.

  4. Use the ETMOSSRR to restore the ETM registers from memory. See OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later.

  5. Clear the OS Lock using the ETMOSLAR. See OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later.

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