4.3.1. Signals

The signals output from the ETM are described in:

ETMv1.x and ETMv2.x signals

The following signals are output from the ETM:

PIPESTAT

Pipeline status. These are output on the pipeline status pins, three for ETMv1.x and four for ETMv2.x.

TRACEPKT

Trace packets. These are output on an n-pin trace packet port, where n can be 4, 8, or 16 pins.

TRACESYNC

A trace synchronization signal (ETMv1.x only).

TRACECLK

The same frequency as the processor clock.

The pipeline status signals provide a cycle-by-cycle indication of what is happening in the Execute stage of the processor pipeline. The n-pin trace packet port provides additional information associated with particular pipeline status events. For example, if a change in instruction flow occurs then it is necessary to output the destination address through the n-pin trace packet port. If the processor has executed an instruction that has failed its condition codes (almost all ARM instructions are conditional), no additional data is required through the trace packet port.

Separating the cycle-accurate pipeline status from the trace packets enables the use of an on-chip FIFO for the trace packet information. You can use the FIFO to buffer trace packets, for example when several branches occur in quick succession. You can pass buffered packets out through the port when the processor is executing several sequential instructions that have no trace packets associated with them. This technique enables the use of a trace port that has a lower data bandwidth than the maximum peak bandwidth.

The width of the trace packet port is determined by the bandwidth of data trace that you require:

  • You can use a 4-pin port when the number of data accesses to be traced is relatively low.

  • The 8-pin and 16-pin variations of the port are more suitable when medium or high numbers of data accesses must be traced to provide the required debugging capabilities.

Using the on-chip FIFO means that a particular pipeline status event and its associated trace packet (or packets) might not appear in the same cycle. A mechanism is provided to ensure synchronization of the two streams of information. For more information:

ETMv3.x signals

The following signals are output from the ETM:

TRACECLK

The trace port must be sampled on both edges of this clock. There is no requirement for this to be linked to the core clock.

TRACEDATA[n-1:0]

This signal can be any size. If this is not a multiple of 8 bits then some realignment might be required in the decompressor. See A-sync, alignment synchronization for more information.

TRACECTL

This signal indicates whether trace can be stored this cycle, in conjunction with TRACEDATA[0]. This signal does not have to be stored.

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