5.1.1. Trigger PIPESTAT signals

Rather than having a dedicated pin to indicate a trigger event, a special pipeline status encoding is used.

When a trigger event occurs, the TR (Trigger) pipeline status replaces the current pipeline status and the pipeline status that is replaced is output on the TRACEPKT[2:0] pins. The FIFO draining is stopped for that cycle to enable this to happen, and the decompressor must take account of this.

To ensure that trace trigger events can be used to trigger external logic, such as a logic analyzer, it is important that generation of the TR pipeline status is not delayed. The TR pipeline status must be generated as soon as possible after the trigger event goes active. This means that a TR can occur before the instruction that caused it is traced.

Note

Trace discontinuities result in an imprecise the trigger condition. They can be caused by overflow of the FIFO, or TraceEnable going inactive. Therefore, decompression of the trace does not associate the trigger with a particular processor cycle. In addition, if an instruction causes the trigger to occur, the trigger status might not be generated on the pipeline status for that instruction.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211