5.5.4. Compressed branch address packet structure

When a processor performs a branch operation the destination of the branch is often reasonably close to the current address. The spatial locality of branch destinations provides additional compression of the branch addresses. It is necessary to output only the low order bits that have changed since the last branch. The full address can be reconstructed when decompression of the trace information takes place.

All trace packets are eight bits in length and a branch address can be made up of between one and five packets. The TRACESYNC signal indicates the first packet and is asserted HIGH only for the first packet of any branch address.

Each packet of a branch address is structured so that the most significant bit (bit [7]) indicates if there are more address packets. This makes it possible for the decompressor to detect the last packet. If bit [7] is HIGH, another address packet follows. Bit [7] LOW means it is the last address packet.

To decide how many packets are required, the on-chip logic registers the last branch address that it has output, and when another branch occurs, the new address is compared with the one that was previously output. Only sufficient low order bits must be output to cover all the bits that have changed in the address. For example, if the upper 12 bits of the address are unchanged and A[19] is the most significant bit to have changed, then it is only necessary to output A[19:0]. You can do this in three address packets instead of five.

A full 32-bit address is made up of five packets. In ARM and Thumb state, the first four have bit [7] HIGH and the last packet has bit [7] LOW. The address is made up as follows:

Address[6:0]

Bits [6:0] of first packet, bit [7] HIGH.

Address[13:7]

Bits [6:0] of second packet, bit [7] HIGH.

Address[20:14]

Bits [6:0] of third packet, bit [7] HIGH.

Address[27:21]

Bits [6:0] of fourth packet, bit [7] HIGH.

Address[31:28]

Bits [3:0] of last packet, bit [7] LOW.

This is shown in Figure 5.1.

Figure 5.1. Full address output in ARM and Thumb state

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Note

When an address is output that is less than 32 bits the new address value replaces the appropriate bits in the previously output branch address. The value does not have to be added to or subtracted from the previous value, nor is it based on the immediately preceding PC value.

Moving to and from Jazelle state (ETMv1.3 only)

When in Jazelle state or moving to and from Jazelle state, bit [7] of the fifth address packet is used as follows:

Bit [7] asserted

When branching into Jazelle state.

Bit [7] cleared

When branching into ARM/Thumb state.

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