3.2.6. Synchronization of ETM register updates

Software running on the processor can program the debug registers through at least one of:

It is implementation defined which interfaces are implemented.

For the CP14 coprocessor interface, the following synchronization rules apply:

For the memory-mapped interface, the following synchronization rules apply:

Some memory-mapped ETM registers are not idempotent for reads or writes. Therefore, the region of memory occupied by the ETM registers must not be marked as Normal memory, because the Memory Order Model permits accesses to Normal memory locations that are not appropriate for such registers. Memory used for memory-mapped ETM registers must have the Strongly-ordered or Device attribute, otherwise the effects of accesses to the registers are unpredictable.

Synchronization between register updates made through the external debug interface and updates made by software running on the processor is implementation defined. However, if the external debug interface is implemented through the same port as the memory-mapped interface, then updates made through the external debug interface have the same properties as updates made through the memory-mapped interface.

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