8.2.6. Signal descriptions

For details of the TRACECLK, TRACESYNC, PIPESTAT, and TRACEPKT output signals, see Chapter 4 Signal Protocol Overview.

The following sections describe the signals on the target connector pins:

EXTTRIG input

EXTTRIG is an optional signal. It is intended to be an input to one of the external inputs on the ETM. Depending on the design, ETM external triggers might not be available on the ASIC external pins. In this case the EXTTRIG has no function. ARM recommends that this pin is pulled to a defined state.

VTRef output

The VTRef signal is intended to supply a logic-level reference voltage to enable debug equipment to adapt to the signalling levels of the target board. It does not supply operating current to the debug equipment. Target boards must supply a voltage that is nominally between 1V and 5V. With ±10% tolerance, this is minimum 0.9V, maximum 5.5V. The target board must provide a sufficiently low DC output impedance so that the output voltage does not change by more than 1% when supplying a nominal signal current (±0.4mA). Debug equipment that connects to this signal must interpret it as a signal rather than a power supply pin and not load it more heavily than a signal pin. The recommended maximum source or sink current is ±0.4mA.

VSupply output

The VSupply signal enables the target board to supply operating current to debug equipment so that an additional power supply is not required. This might not be used by all debug equipment. The VDD power rail typically drives the pin on the target board. Target board documentation must indicate the VSupply pin voltage and the current available. Target boards must supply a voltage that is nominally between 2V and 5V. With ±10% tolerance, this is minimum 1.8V, and maximum 5.5V. A target board that drives this pin must provide a minimum of 250mA, and 400mA is recommended. Debug equipment must indicate the required supply voltage range and the current consumption over that range. This enables you to determine whether an external power supply is required to power the debug equipment. Target boards might have a limited amount of current available for external debug equipment, so a backup mechanism to power the debug equipment must be provided where VSupply is not connected, or is insufficient. For some hardware, this signal is unused.

nTRST input

The nTRST signal is an open collector input from the run control unit to the Reset signal on the target JTAG port. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

Note

Board logic must ensure that there is a LOW pulse on the nTRST pin of the target ASIC at power up.

TDI input

TDI is the Test Data In signal from the run control unit to the target JTAG port. ARM recommends that you pull this pin to a defined state.

TMS input

TMS is the Test Mode Select signal from the run control unit to the target JTAG port. This pin must be pulled up on the target so that the effect of any spurious TCKs when there is no connection is benign.

TCK input

TCK is the Test Clock signal from the run control unit to the target JTAG port. ARM recommends that this pin is pulled to a defined state.

RTCK output

RTCK is the Return Test Clock signal from the target JTAG port to the run control unit. Some targets, such as ARM7TDMI-S™ processor, must synchronize the JTAG port to internal clocks. To assist in meeting this requirement, you can use a returned (and re-timed) TCK to dynamically control the TCK rate.

TDO output

This signal is the Test Data Out from the target JTAG port to the run control unit.

nSRST input

This is an open collector output from the run control unit to the target system reset. This might also be an input to the run control unit so that a reset initiated on the target can be reported to the debugger.

You must pull this pin HIGH on the target to avoid unintentional resets when there is no connection.

DBGRQ input

The DBGRQ signal is used by the run control unit as a debug request signal to the target processor. ARM recommends that this pin is pulled to a defined state. This signal is rarely implemented as a pin on the target ASIC. Use of this pin is not recommended for the dual-target connector.

You must pull this pin LOW on the target to avoid unintentional debug requests when there is no run control unit connected.

DBGACK output

The DBGACK signal is used by some run control units to detect entry or exit from debug state. This signal is rarely implemented as a pin on the target ASIC. Use of this pin is not recommended for the dual-target connector.

VDD input

VDD is a logic level 1 signal for compatibility with TPAs designed for ETMv1 or ETMv2 only. It is normally equivalent to VTRef.

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