2.7.4. Exact matching, in ETMv2.0 and later

This section describes exact matching in ETMv2.0 and later, where exact matching is controlled by a bit in the ETMACTR. For information about exact matching in ETMv1.x see Exact matching, in ETMv1.x.

The Exact match bit is bit [7] of the ETMACTR. In ETMv2.0 and later you can set the Exact match bit to 1 to enable the comparator to match later, as described in this section. This late matching can improve accuracy in the comparison. For example, in the case of out-of-order data it enables the comparator to wait until the result of the data value comparison is known before matching. The functionality of the Exact match bit depends on:

Use of a comparator with the Exact match bit set to 1 in the programming of TraceEnable or ViewData results in Imprecise Tracing.

In general, the Exact match bit is set to 1 when the comparator is used by a derived resource, and set to 0 when the comparator is used directly as an include/exclude region.

From ETMv3.3, setting the Exact match bit affects the holding behavior of the address range comparators. See Behavior of address comparators for more information.

Exact matching behavior for the different access types is described in the following sections:

Exact matching for instruction address comparisons

For Execute-stage instruction address comparisons, the behavior of the Exact match bit depends on whether the instruction is canceled because of an exception. This is shown in Table 2.2.

Table 2.2. Effect of exact match bit settings for instruction address comparisons

Exact match bit valueInstruction canceledInstruction not canceled

0

Comparator matchesComparator matches

1

Comparator does not matchComparator matches

For Fetch stage instruction address comparisons, the Exact match bit is ignored. Canceled instructions can cause the comparator to match.

In Jazelle state, the comparator matches at the beginning of the bytecode if the Exact match bit is set to 0, and at the end of the bytecode if the Exact match bit is set to 1. This enables the comparator to wait until it knows whether or not the bytecode was interrupted.

Whenever an instruction is considered for tracing, because TraceEnable enables tracing, the ETM must compare the instruction address with the address comparators. For example, an ETM can trace a prefetch abort in either of two ways:

  • the instruction that prefetch aborts is traced and then a prefetch abort exception indicates that the instruction is canceled

  • the instruction that prefetch aborts is not traced and the prefetch abort exception is non-cancelling.

When a prefetch abort is traced as cancelling, the comparators compare the address of the instruction that prefetch aborted. The exact match bit is used here to ensure that the comparator only matches when the prefetch abort does not occur. When traced as non-cancelling, the ETM does not have the address of the prefetch aborted instruction because the instruction is not traced, so the comparators do not compare based on this address and never match.

Exact matching for data address comparisons

This section describes exact matching behavior on accesses to data addresses, whether or not data value comparison is enabled for the access. For additional information about comparator behavior when data value comparisons are enabled see Operation of data value comparators.

The rules for data address comparisons are fairly complex, and depend on:

  • Whether the comparison is on a normal transfer, or on an out-of-order transfer.

    • In ETMv3.0 and earlier, matching behavior on an out-of-order transfer is different to the behavior in ETMv3.1 and later.

  • The setting of these fields in the ETMACTR:

    • data value comparison control field, bits [6:5]

    • exact match bit, bit [7].

    For more information see Address Comparator Access Type Registers, ETMACTRn.

  • Whether the data value matches the comparison value held in the ETMDCVR. This data value comparison is masked with the value held in the ETMDCMR. For more information see About the data value comparator registers.

  • Whether the data transfer:

    • causes a synchronous data abort

    • is a failed store-exclusive transfer.

    Synchronous data aborts and failed store-exclusive transfers have the same effect on the data value comparison.

Table 2.3 shows the data comparison results for normal transfers, and Table 2.4 shows the results for comparisons on out-of-order transfers. In all cases, the final comparator result is the logical AND of the result from one of these tables with the result of the associated address comparison.

For more information about the effect of the value of the Exact match bit see Additional details of the effect of the Exact match bit.

Table 2.3. Data value comparisons for normal transfers

ETMACTR values:Data comparison result when:
DCompare mode[a]Exact match bit[b]Transfer aborts or is a Store fail[c]Data value matchesData value does not match
No data value comparison0111
No data value comparison1011
Data value matches0110
Data value matches1010
Data value does not match0101
Data value does not match1001

[a] Data compare mode, bits [6:5] of the ETMACTR. See Address Comparator Access Type Registers, ETMACTRn. The permitted values are:

          b00: no data value comparison is made

          b01: comparator can match only if Data value matches

          b11: comparator can match only if Data value does not match.

[c] Values in this column apply if the transfer causes a synchronous data abort or is a Store Exclusive that fails. The result is not affected by the value of the data associated with the transfer.


Note

From the table, notice that if the Exact match bit is not set to 1, a data comparison match is generated by:

  • a transfer that causes a synchronous data abort

  • a store-exclusive that fails.

Table 2.4. Data value comparisons on an out-of-order transfer

ETMACTR values:Data comparison result when:
DCompare mode[a]Exact match bit[b]Transfer aborts or is a Store fail[c]Data value matchesData value does not match
No data value comparison0111
No data value comparison10[d]1[d]1[d]
Data value matches0111
Data value matches10[e]1[e]0[e]
Data value does not match0111
Data value does not match10[e]0[e]1[e]

[a] Data compare mode, bits [6:5] of the ETMACTR. See Address Comparator Access Type Registers, ETMACTRn. The permitted values are:

          b00: no data value comparison is made

          b01: comparator can match only if Data value matches

          b11: comparator can match only if Data value does not match.

[c] Values in this column apply if the transfer causes a synchronous data abort or is a store-exclusive that fails. The result is not affected by the value of the data associated with the transfer.

[d] In ETMv3.1 and later, the comparator waits for the out-of-order data to return, and then gives the result shown.

In ETMv3.0 and earlier, the result is returned immediately, and is always 1.

[e] The comparator waits for the out-of-order data to return and then gives this result.


Note

From the table, notice that if the Exact match bit is not set to 1, the data value comparator always reports a match when an out-of-order transfer occurs.

Additional details of the effect of the Exact match bit
Exact match bit set to 0 (default setting)

When an out-of-order transfer, synchronous data abort, or Store Exclusive fail occurs, the comparator matches immediately. This means that tracing of out-of-order transfers, data aborts and Store Exclusive fails is based on the data address only, because the data value is assumed to be invalid.

Tracing out-of-order transfers based on the address alone is useful when the comparator is used for trace filtering, if you do not mind generating some additional trace that you do not require.

Exact match bit set to 1

When an out-of-order transfer occurs, the comparator waits for the data value to be returned, then matches if the data value matches.

Waiting for the data value compare to occur is useful when data values are used by derived resources to create triggers and other events.

Waiting for the data value compare to occur causes the out-of-order transfer to be missed if the comparator is used directly as an include region by TraceEnable or ViewData. Because out-of-order data is traced only if the out-of-order placeholder is traced, the result of having the exact match bit set to 1 is that the data is not traced even if it matches.

When a data abort or a Store Exclusive fail occurs, the comparator does not output a match regardless of whether or not a data value comparison is requested. This behavior is often preferred when a comparator is meant to match only once, because aborted accesses are usually re-attempted when the condition causing the abort condition has been resolved.

When counting the execution of load or store instructions, the occurrence of data aborts and the subsequent retrying of instructions causes the instruction count to be larger than expected.

Note

Using data values to create an event, such as a sequencer transition, can result in out-of-order events occurring because the data might be returned out-of-order. If you are concerned that the nonblocking cache might affect programmed events, you can disable it in the processor. For more information, see the Technical Reference Manual for your processor.

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