3.5.28. Counter Enable Registers, ETMCNTENRn

The ETMCNTENR characteristics are:

  • defines the event that enables the corresponding counter

  • can be used to configure the counter for continuous operation.

Usage constraints

Each ETMCNTENR is used with a corresponding ETMCNTRLDVR, ETMCNTRLDEVR, and ETMCNTVR. See About the counter registers.


The number of ETMCNTENRs

  • is implementation defined

  • is specified by ETMCCR bits [15:13]

  • can be zero.

See Configuration Code Register, ETMCCR.

Unimplemented ETMCNTENRs are RAZ/WI.


See the register summary in Table 3.3, and Reset behavior.

Figure 3.27 shows the ETMCNTENR bit assignments, for ETM version 2.0 or later.See Table 3.38 for the differences in other architecture versions.

Figure 3.27. ETMCNTENR bit assignments

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Table 3.38 shows the ETMCNTENR bit assignments, and describes the differences in different ETM architecture versions:

Table 3.38. ETMCNTENR bit assignments


Version [a]




v1.x only

Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and decrements every cycle regardless of the count enable event. When set to 1, the count enable event is used to enable the counter. ARM recommends that bit [17] is always set to 1 and that the count enable event is used to control counter operation, using 0x6F (TRUE) if a free running counter is required.


This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM architecture versions.



Count enable event.

To configure a continuous counter, program these bits for external resource 15. See Resource identification. External resource 15 is hard-wired to be always active.

[a] The first ETM architecture version that defines the field, or (where the use of a field is different in different versions) the first architecture version to which the description applies.

Each ETMCNTENR has the same bit assignments.

Using ETM event resources describes how you define a counter enable event.

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