3.5.14. FIFOFULL Level Register, ETMFFLR

The ETMFFLR characteristics are:

Purpose

Holds the level below which the FIFO is considered full, although its function varies for different ETM architectures.

From ETMv3.0 the value in this register also controls the point at which data trace suppression occurs.

Usage constraints

The access type of this register depends on the ETM architecture version. See Table 3.3.

Configurations

This register is available in all ETM implementations.

Attributes

See the register summary in Table 3.3, and Reset behavior.

Figure 3.16 shows the ETMFFLR bit assignments.

Figure 3.16. ETMFFLR bit assignments

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Table 3.22 shows the ETMFFLR bit assignments.

Table 3.22. ETMFFLR bit assignments

Bits

TypeVersion [a]

Description

[31:8]--Reserved.
[7:0]

WO

v1.0

The number of bytes left in the FIFO, below which the FIFOFULL or SuppressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO.

RWv2.0

[a] The first ETM architecture version to which the Type value applies.


The maximum valid value for this register is the size of the FIFO. This causes FIFOFULL to be asserted whenever the FIFO is not empty. Behavior is unpredictable if the value 0 is written to this register and Stall processor or Suppress data (ETMv3 only) is selected in the ETMCR, register 0x000:

ETMv1.x

If a value larger than the FIFO size is written to the ETMFFLR, the behavior is unpredictable. It is not possible to determine the FIFO size from the programmers’ model.

ETMv2.x

Depending on the implementation, your ETM might not observe the ETMFFLR. If it does not, the ETM assumes that the FIFOFULL level is always set to its maximum value (see Processor stalling, FIFOFULL). This enables it to assert FIFOFULL earlier because no comparison with the FIFO level is required. In this case the ETMFFLR ignores writes, and returns the FIFO size when read.

If a value larger than the FIFO size is written to the ETMFFLR, the FIFO size itself is selected, and is the value returned when the register is read.

You must determine:

  • the size of the FIFO

  • whether the ETM ignores the ETMFFLR.

To do this you must perform the following sequence of operations:

  1. Write the value 0xFFFFFFFF to the register.

  2. Read the register. The value returned is the FIFO size.

  3. Write the value 0x00000001 to the register.

  4. Read the register.

    If 0x00000001 is returned, the ETM observes this register.

    If the same value is returned as in step 2, the ETM ignores this register.

ETMv3.0 and later

For processors that choose to implement it, data suppression is offered in addition to or instead of FIFOFULL. The ETMFFLR is used for both. The modes supported are listed in Table 3.23. See Data suppressed packet for more information on data suppression.

If a value larger than the FIFO size is written to the ETMFFLR, the FIFO size itself is selected, and is the value returned when the register is read.

The ETM asserts FIFOFULL only when both these bits are set to 1.

Table 3.23. Supported FIFOFULL and data suppression modes in ETMv3.0 and later

Stall processor [a]

Suppress data [b]

Description
00No overflow avoidance.
10FIFOFULL is asserted when the number of free bytes in the FIFO is less than the value in the ETMFFLR, subject to the FIFOFULL region if present.
01Data suppression occurs if the data causes the number of free bytes in the FIFO to be less than the value in the ETMFFLR. This is not subject to the FIFOFULL region.
11unpredictable.

[a] Controlled by ETMCR bit [7]. See Main Control Register, ETMCR.

[b] Controlled by ETMCR bit [18]. See Main Control Register, ETMCR.


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