3.5.38. Implementation specific registers

Register numbers 0x70-0x77 in the register map are reserved for the future implementation of up to eight application-specific registers. Even when an ETM does not implement these registers, implementation specific Register 0, register number 0x70, must be partially defined, so that a debugger can implement a general mechanism for detecting implementation specific extensions.

See Table 3.3 for details of access to this register area.

Implementation specific Register 0

The implementation specific Register 0 characteristics are:


Shows the presence of any implementation specific features, and enables any features that are provided.

Usage constraints

There are no usage constraints.


This register is only available in ETMv2.0 or later, and must be implemented in those ETM versions.


See the register summary in Table 3.3 and Reset behavior.

Figure 3.35 shows the implementation specific Register 0 default bit assignments.

Figure 3.35. implementation specific Register 0 bit assignments

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Table 3.48 shows the implementation specific Register 0 default bit assignments.

Table 3.48. implementation specific Register 0 default bit assignments

BitsVersion [a]TypeDescription
[7:4]v2.0RW [b]

Enable implementation specific extensions. The ETM must behave as if the implementation specific extensions are not implemented when these bits are b0000. The behavior of the ETM is implementation defined when these bits are set to any value other than b0000.

On an ETM reset these bits are cleared to b0000.

[3:0]v2.0ROIf this field is b0000 then no implementation specific extensions are supported. Other values are for use only as permitted in writing by ARM Limited.

[a] The first ETM architecture version that defines the field.

[b] RW only if bit [11] of the ETMCCER is set to 1, RO otherwise. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.


Trace debug tools might require application-specific modifications to support any added functionality.

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