3.5.27. Counter Reload Value Registers, ETMCNTRLDVRn

The ETMCNTRLDVR characteristics are:


Specifies the starting value of the corresponding counter.

Usage constraints

Each ETMCNTRLDVR is used with a corresponding ETMCNTENR, ETMCNTRLDEVR, and ETMCNTVR. See About the counter registers.


The number of ETMCNTRLDVRs:

  • is implementation defined

  • is specified by ETMCCR bits [15:13].

  • can be zero.

See Configuration Code Register, ETMCCR.

Unimplemented ETMCNTRLDVRs are RAZ/WI.


See the register summary in Table 3.3, and Reset behavior.

Figure 3.26 shows the ETMCNTRLDVR bit assignments.

Figure 3.26. ETMCNTRLDVR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.37 shows the ETMCNTRLDVR bit assignments.

Table 3.37. ETMCNTRLDVR bit assignments


Defined in ETM architecture versions




v1.0 and later

Initial count

Each ETMCNTRLDVR has the same bit assignments.

If an ETMCNTRLDVR is programmed when the ETM Programming bit is set, the corresponding counter is loaded with the value written to the register. The counter is then reloaded with this value whenever the corresponding counter reload event, specified by the ETMCNTRLDEVR, is active.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q