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The ETMCNTRLDVR characteristics are:
Specifies the starting value of the corresponding counter.
Each ETMCNTRLDVR is used with a corresponding ETMCNTENR, ETMCNTRLDEVR, and ETMCNTVR. See About the counter registers.
The number of ETMCNTRLDVRs:
is implementation defined
is specified by ETMCCR bits [15:13].
can be zero.
See Configuration Code Register, ETMCCR.
Unimplemented ETMCNTRLDVRs are RAZ/WI.
See the register summary in Table 3.3, and Reset behavior.
Figure 3.26 shows the ETMCNTRLDVR bit assignments.
Table 3.37 shows the ETMCNTRLDVR bit assignments.
Table 3.37. ETMCNTRLDVR bit assignments
Bits | Defined in ETM architecture versions | Description |
|---|---|---|
| [31:16] | - | Reserved |
[15:0] | v1.0 and later | Initial count |
Each ETMCNTRLDVR has the same bit assignments.
If an ETMCNTRLDVR is programmed when the ETM Programming bit is set, the corresponding counter is loaded with the value written to the register. The counter is then reloaded with this value whenever the corresponding counter reload event, specified by the ETMCNTRLDEVR, is active.
| Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. | ARM IHI 0014Q |
| Non-Confidential | ID101211 |
| PDF version | |
| Home > Programmers’ Model > Detailed register descriptions > Counter Reload Value Registers, ETMCNTRLDVRn |