3.5.40. ID Register, ETMIDR, ETMv2.0 and later

The ETMIDR characteristics are:

Purpose

Holds the ETM architecture variant, and defines the programmers’ model for the ETM.

Usage constraints

This register is valid only when bit [31] in the ETMCCR is set to 1. See Configuration Code Register, ETMCCR. When bit [31] in the ETMCCR is set to 0 the ETMCCR holds the ETM architecture version.

Configurations

This register is only available in ETMv2.0 and later.

Attributes

See the register summary in Table 3.3 and Reset behavior.

Figure 3.37 shows the ETMIDR bit assignments, for ETM architecture version 3.4. See Table 3.50 for the differences in other architecture versions.

Figure 3.37. ETMIDR bit assignments, for ETM architecture v3.4

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Table 3.50 shows the ETMIDR bit assignments, and describes the differences between different ETM architecture versions.

Table 3.50. ETMIDR bit assignments

Bits

Version [a]

Description

[31:24]

v2.0

Implementer code. The following codes are defined [b], all other values are reserved by ARM Limited:

0x41

ASCII code for A, indicating ARM Limited.

0x44

ASCII code for D, indicating Digital Equipment Corporation.

0x4D

ASCII code for M, indicating Motorola, Freescale Semiconductor Inc.

0x51

ASCII code for Q, indicating QUALCOMM Inc.

0x56

ASCII code for V, indicating Marvell Semiconductor Inc.

0x69

ASCII code for i, indicating Intel Corporation.

[23:21]

-

Reserved.

[20]v3.4

Branch packet encoding implemented. The possible values of this bit are:

0

The ETM implements the original branch packet encoding. See Branch packet formats with the original address encoding scheme.

1

The ETM implements the alternative branch packet encoding. See Branch packet formats with the alternative address encoding scheme.

[19]

v3.2

Support for Security Extensions. The possible values of this bit are:

0

The ETM behaves as if the processor is in Secure state at all times.

1

The ARM architecture Security Extensions are implemented by the processor.

[18]v3.2

Support for 32-bit Thumb instructions. The possible values of this bit are:

0

A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions.

1

A 32-bit Thumb instruction is traced as a single instruction. See 32-bit Thumb instructions for more information.

[17]-

Reserved.

[16]v2.1

Load PC first. If this bit is set to 1, LSMs with the PC in the list load the PC first, followed by the other registers in the normal order. This can be decompressed by using the following procedure:

  1. Calculate the number of items transferred by the LSM by looking at the code image.

  2. As each item is read, assign an address equal to 4 greater than the previous one as normal.

  3. When the number of items read equals the total number of items transferred, subtract (4 * number of items) from each address other than the first.

Note

This means that a branch address can be traced before the remaining data values of an instruction. While this has never been prohibited in the protocol, care must be taken to ensure that this case is correctly handled.

[15:12]

v2.0

Processor family. The meaning of this field depends on the value of the Implementer code.The following apply if Implementer code = 0x41, for ARM Limited:

b0000

ARM7 processor.

b0001

ARM9 processor.

b0010

ARM10 processor.

b0011

ARM11 processor

b1111

Processor family is defined elsewhere. See The Processor family field for more information.

When the Implementer code = 0x41, all other values are reserved by ARM Limited.

For any other Implementer code the permitted values of this field are defined by the implementer.

[11:8]

v2.0

Major ETM architecture version number. See The ETM architecture version. Possible values of this field are:

b0000

ETMv1.

b0001

ETMv2.

b0010

ETMv3.

All other values are reserved.

[7:4]

v2.0

Minor ETM architecture version number. See The ETM architecture version.

[3:0]

v2.0

Implementation revision. See Implementation revision

[a] The first ETM architecture version that defines the field.

[b] The Implementer code list applies to processors and to ETMs. This list does not indicate the implementer of ETMs.


The ETM architecture version

In the ETMIDR, the ETM architecture version is encoded as ETMvX.Y, where:

  • (X-1) = the value encoded in register bits [11:8]

  • Y = the value encoded in register bits [7:4].

For protocol versions up to 3, previous versions of this specification referred to protocol numbers and made no reference to ETMv2. To enable independent evolution of ETMs in different product families and to provide better information to tools using the ETM, protocol numbers are replaced with major and minor architecture version numbers. If a protocol number is referred to as a characteristic of an ETM implementation, the major architecture version of that implementation is 1.

An ETMIDR value of zero indicates that the ETM is not present. This can be returned by the coprocessor interface in processors supporting ARMv6 and later.

Table 3.51 shows the ETMIDR values for ETMs described in this specification and implemented by ARM Limited.

Table 3.51. ID values for different ETM variants

ImplementationID value

Architecture version

Protocol number (deprecated)

ETM not present0x00000000[a]--
ETM7 Rev 00x41000010[b]ETMv1.11
ETM7 Rev 10x41000020[b]ETMv1.22
ETM7 Rev 1a0x41000021[b]ETMv1.24
ETM9 Rev 00x41001000[b]ETMv1.00
ETM9 Rev 0a0x41001010[b]ETMv1.11
ETM9 Rev 10x41001020[b]ETMv1.22
ETM9 Rev 20x41001030[b]ETMv1.33
ETM9 Rev 2a0x41001031[b]ETMv1.35
ETM9 r2p20x41001032[b]ETMv1.37
CoreSight ETM9 r0p00x41001220ETMv3.2-
ETM10 Rev 00x41002100ETMv2.0-
ETM10RV Rev 00x41002200ETMv3.0-
ETM11RV r0p00x41003210[c]ETMv3.1-
ETM11RV r0p10x41013211ETMv3.1-
CoreSight ETM11 r0p0

0x41013220

0x41053220

0x41093220

ETMv3.2-
CoreSight ETM-A50x410CF250ETMv3.5-
CoreSight ETM-A70x410CF250ETMv3.5-
CoreSight ETM-A80x410CF230ETMv3.3-
CoreSight ETM-R40x4104F230ETMv3.3-
CoreSight ETM-R50x4104F230ETMv3.3-
CoreSight ETM-M30x4114F240ETMv3.4-
CoreSight ETM-M40x4114F250ETMv3.5-

[a] Returned from CP14 access.

[b] These ETMs do not have an ETMIDR. Bit [31] of the ETMCCR is 0 and the minor architecture version number is given in that register. See Table 3.12 for more information. The value provided here is for illustration.

[c] Bit [16], Load PC first, is not set to 1 in this revision, but the revision has the behavior associated with having bit [16] set to 1. That is, LSMs with the PC in the list load the PC first.


Note

Tools must determine the programmers’ model from the major and minor architecture version numbers alone where possible. The Processor family field must not be used to determine aspects of ETM behavior.

The Processor family field

From ETMv3, where the Implementer code field, bits [31:24], is 0x41, ARM Limited recommends that debug tools do not use the Processor family field, bits [15:12], to discover information about the connected processor. Instead, the tools must interrogate the processor directly, for example by reading its identification registers. See the Technical Reference Manual of the appropriate processor for more information.

From ETMv3.3, macrocells implemented by ARM Limited normally return 4'b1111 in this field, meaning that the processor family is identified elsewhere.

Note

To find the processor family, you can read the JTAG IDCODE of the processor, if this feature is implemented. See the Technical Reference Manual for the processor for more information.

Implementation revision

ETMv3.4 required that the revision field in the ETMIDR and ETMPIDR2 be identical. In ETMv3.5:

  • ETMPIDR2 identifies the revision of the external debugger and memory mapped interfaces

  • ETMIDR identifies the revision of the Trace registers and the OS Save/Restore registers.

ARM recommends that implementations keep these values identical to ensure revision numbers can be managed easily, however in cases where an ECO fix is required and changing both revisions is difficult, it is acceptable to change the revision fields independently.

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