3.5.39. Synchronization Frequency Register, ETMSYNCFR, ETMv2.0 and later

The ETMSYNCFR characteristics are:

Purpose

Holds the trace synchronization frequency value.

Usage constraints

There are no usage constraints.

Configurations

This register is only available in ETMv2.0 and later.

Attributes

See:

  • the register summary in Table 3.3

  • the register description for more information about the RO implementation option

  • Reset behavior.

Figure 3.36 shows the ETMSYNCFR bit assignments, with the default value of the register:

Figure 3.36. ETMSYNCFR bit assignments

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Table 3.49 shows the ETMSYNCFR bit assignments.

Table 3.49. ETMSYNCFR bit assignments

Bits

Defined in ETM architecture versions

Description

[31:12]-Reserved.

[11:0]

v2.0 and later

Synchronization frequency. Default value is 1024.


In ETMv2.0 and later, when a Trace FIFO Offset (TFO) has occurred, the TFO counter is reset to the value that is programmed into the ETMSYNCFR. This value is the time between synchronization points in the trace (the tools can start decompressing only at synchronization points). Depending on the protocol version, the time is measured in cycles or bytes. The default value is 1024.

For ETMv3.4 and earlier, this value must be set to a value greater than the size of the FIFO.

In ETMv3.5, this value must be set to a value greater than the size of the FIFO, or to zero. Values greater than zero but less than the FIFO size are still not permitted.

A value of zero disables periodic synchronization based on the synchronization frequency counter. This does not affect other sources of synchronization, such as external requests from a CoreSight system.

The ETM must always perform full synchronization when any of the following occur:

An implementation might not implement the bottom bits of this register, because of limitations in the accuracy of the synchronization frequency. In this case, a value read from this register might be different from the value written to it.

From ETMv3.4, an ETM implementation can implement a fixed synchronization frequency of 1024. In this case the ETMSYNCFR is implemented as a read-only register, that always returns the value 1024 (0x00000400) on reads. For more information see Finding the access type, ETMv3.4 and later.

This register is used to control TFOs in ETMv2. See Trace FIFO offsets. This register is used to control A-sync, I-sync, and D-sync in ETMv3. See Synchronization.

Finding the access type, ETMv3.4 and later

From ETMv3.4, the ETMSYNCFR can be implemented as either:

To find out how the register is implemented, in ETMv3.4 or later:

  1. Make sure that bit [11] of the ETMCCER is set to 1. This means that, if the implementation permits the Synchronization Frequency to be changed, you can write to the ETMSYNCFR.

  2. Read the value of the ETMSYNCFR. You might have to restore this value later.

  3. Write the value 0xFFFFFFFF to the ETMSYNCFR.

  4. Read the value of the ETMSYNCFR again:

    • If this value is 0x00000400 then the register is implemented as read-only.

    • If the value is not 0x00000400 then the register is implemented as read/write, write only if bit [11] of the ETMCCER is set to 0.

      Note

      When the register is implemented as read/write, it is still unlikely that this second read of the register returns 0xFFFFFFFF, because:

      • bits [31:12] of the register are reserved and might read-as-zero

      • the bottom bits of the register might not be implemented.

      Your check must not expect the read at stage 4 to match the value written at stage 3.

  5. If the ETMSYNCFR is implemented as read/write, write the value from stage 2 back to the register.

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