3.5.35. About the Context ID comparator registers, ETMv2.0 and later

From ETMv2.0, an ETM can implement up to three Context ID comparators. The ETM implements a value register for each Context ID comparator, and a single mask register that applies to all of the Context ID comparators. Table 3.45 shows these registers:

Table 3.45. Context ID comparator registers

DescriptionRegister numberOffset [a]
Context ID Comparator Value 1 Register, ETMCIDCVR10x06C0x1B0
Context ID Comparator Value 2 Register. ETMCIDCVR20x06D0x1B4
Context ID Comparator Value 3 Register. ETMCIDCVR30x06E0x1B8
Context ID Comparator Mask Register, ETMCIDCMR0x06F0x1BC

[a] When accessed in a memory-mapped scheme, the register offset is always (4 x (Register number)).


These registers are write-only, although in architecture versions 3.1 and later they are read/write when bit [11] of the ETMCCER is set to 1. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

The following sections describe these registers:

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211