2.6.4. TraceEnable and filtering the instruction trace

The trace port uses the TraceEnable signal to turn tracing on and off during a trace run.

TraceEnable is generated by:

Figure 2.5. TraceEnable configuration

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The operating mode, include or exclude, is defined statically for each trace run. Mixing include and exclude regions is not supported. Figure 2.5 shows the structure of the TraceEnable signal.

An exclude region is useful for excluding library code or particular functions that are known to generate a lot of data.

An include region enables all code inside a simple range to be traced, for example the FIQ and IRQ handlers.

You configure the TraceEnable logic by programming the TraceEnable registers as Figure 2.6 shows. For more information, see About the TraceEnable registers.

From ETMv3.3, if the TraceEnable include/exclude function is used to exclude a specific instruction then TraceEnable remains low until the next instruction.

Figure 2.6. Programming the TraceEnable logic

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Data-controlled instruction tracing

You can control instruction tracing using data accesses. This means that you can trace a load or store instruction based on the data accesses that the instruction performs, rather than only on its instruction address. You can configure the access type by setting the access type value in the ETMACTR. See About the address comparator registers.

Note

In ETMv1.x, the data for an LSM instruction is traced if and only if ViewData is active for the first data access in the instruction. If ViewData is active only for the second or subsequent data access, then the instruction is traced as Instruction Executed rather than Instruction with Data.

Caution

  • If data address comparators are used in exclude regions, TraceEnable behavior is unpredictable.

  • If you want to use data address comparisons to define trace exclude regions, use the data address comparators as ETM resources that define the TraceEnable enabling event.

Imprecise TraceEnable events

If TraceEnable is imprecise for any reason, any of the following might occur:

  • tracing might not turn on in time to trace the required instruction

  • tracing might not turn off in time to avoid tracing a specific instruction

  • the data for an instruction might not be traced

  • trace might be missing at the start of a trace region

  • extra trace might appear at the end of a trace region.

With the exception of some implementation defined configurations, the TraceEnable signal is Imprecise if the resource that causes it to change is any of the following:

  • Anything selected by the enabling event

  • An address comparator configured for Fetch-stage instruction addresses

  • An address comparator with its Exact match bit set to 1, ETMv2.0 and later

  • An address comparator configured for data addresses, before ETMv1.2

  • An address comparator connected to a Context ID comparator, where the Context ID changes. This is imprecise for ETMv3.0 and later. It is precise in ETMv2.x.

  • A memory map decoder.

Note

See the appropriate ETM Technical Reference Manual for information about any implementation defined configurations for which the TraceEnable signal is not imprecise.

Rules for the transition of TraceEnable

Transitions of TraceEnable obey the following rules:

  • TraceEnable can transition from LOW to HIGH at any time.

  • When instruction tracing is enabled, TraceEnable can transition from HIGH to LOW only at the end of an instruction. If the processor supports out-of-order data transfers:

    • TraceEnable must remain HIGH until the execution of all outstanding data instructions has completed.

    • If there is no outstanding data instruction, TraceEnable must remain HIGH until the end of the current instruction.

    Note

    Instruction tracing is enabled by default. From ETMv3.1 it can be disabled by setting the Data-only mode bit, bit [20], of the ETMCR to 1. See Main Control Register, ETMCR.

  • When instruction tracing is disabled, TraceEnable can transition from HIGH to LOW at any time.

The trace start/stop block

The trace start/stop block is shown in Figure 2.7. It is only available in ETMv1.2 and later:

  • in ETMv1.2, the trace start/stop block is always present

  • from ETMv2.0, it is optional whether the trace start/stop block is implemented.

Figure 2.7. Trace start/stop block

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From ETMv2.0, the output of the block has two uses, both of which are shown in Figure 2.7, and in Figure 2.5:

  • It provides direct control of TraceEnable operation. This control is gated by the EnOnOff signal, as Figure 2.5 shows. For more information see Using the trace start/stop block to control TraceEnable.

  • It provides an ETM resource, resource type b101 with index b1111 (resource number b101 1111). If the trace start/stop block is implemented this resource is always available, regardless of the state of the EnOnOff signal.

In ETM v1.2, the trace start/stop block does not provide an ETM resource, and the only use of the block is the direct control of TraceEnable.

In all implementations of the trace start/stop block, the address comparators can provide start and stop inputs to the block:

  • Bits [15:0] of the ETMTSSCR define address comparators to use as start addresses for the trace start/stop block. If one of the specified address comparators matches then the trace start/stop block receives a start signal and asserts its output HIGH. The output remains asserted HIGH until the block receives a stop signal.

  • Bits [31:16] of the ETMTSSCR define address comparators to use as stop addresses for the trace start/stop block. If one of the specified address comparators matches then the trace start/stop block receives a stop signal and takes its output LOW. The output remains deasserted (LOW) until the block receives a start signal.

  • The behavior of the trace start/stop block is unpredictable if the same address comparator is used as both the start input and the stop input to the block.

For more information about configuring the ETMTSSCR see TraceEnable Start/Stop Control Register, ETMTSSCR, ETMv1.2 and later.

From ETMv3.4, if an ETM implements any EmbeddedICE watchpoint comparator inputs then those inputs can be used as start and stop inputs to the trace start/stop block. Bit [20] of the ETMCCER indicates that the trace start/stop block can use the EmbeddedICE watchpoint inputs. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later. If this bit is set to 1, bits [7:0] of the TraceEnable Start/Stop EmbeddedICE Control Register specify EmbeddedICE inputs to use as start inputs to the trace start/stop block, and bits [23:16] specify EmbeddedICE inputs to use as stop inputs to the block. For more information see TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR, ETMv3.4.

Note

  • From ETMv3.4, an ETM that does not implement any address comparators might implement a trace start/stop block that only has EmbeddedICE watchpoint comparator inputs.

  • In all earlier ETMs, it is only possible to implement a trace start/stop block on an ETM that includes address comparators, and the address comparators are available as inputs to the trace start/stop block.

When an ETM reset occurs, the state of the trace start/stop logic is reset to the OFF state.

Using the trace start/stop block to control TraceEnable

In ETMv1.2 or later, you can turn instruction tracing on or off whenever certain instructions are executed or when specified data addresses are accessed. This means that you can trace functions, subroutines, or individual variables held in memory.

You can use the trace start/stop block to enable or disable tracing when any single address comparator matches. The effect is precise only if the address comparison is based on instruction execution or data addresses. You can use instruction fetch comparisons, but the effect is not precise.

From ETMv3.4, the EmbeddedICE watchpoint comparator inputs can also be used as inputs to the trace start/stop block, and therefore can be used to enable or disable tracing in the same way as address comparator matches.

The EnOnOff signal, shown in Figure 2.5, determines whether the trace start/stop block controls TraceEnable operation:

EnOnOff LOW:

The state of the trace start/stop logic is ignored, and does not directly control TraceEnable.

Note

The trace start/stop block output is still available as an ETM resource, and can be used to define the TraceEnable enabling event, as Figure 2.5 shows.

EnOnOff HIGH:

TraceEnable is controlled by the trace start/stop block. Tracing only occurs after a start address matches, but before an end address matches. The include/exclude logic still applies. For example, tracing does not occur if the address is in a valid excluded range.

EnOnOff is controlled by bit [25] of the ETMTECR1. See TraceEnable Control 1 Register, ETMTECR1. If you set bit [25] LOW (0), TraceEnable behavior is backwards-compatible with ETM versions 1.0 and 1.1.

Note

  • Comparisons occur sequentially in address order. For every ON comparison there must be a corresponding OFF comparison. If two separate address comparators are set to conflict (one ON, one OFF), then the OFF comparison is ignored.

  • Additional information about the operation of the trace start/stop block is given in Parallel execution.

An example of how to program the TraceEnable logic is given in An example TraceEnable configuration.

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