2.11. Considerations for advanced processors, ETMv2 and later only

As far as possible, the ETM presents the view that all instructions and data transfers occur sequentially. However, this is not always possible where instructions or data transfers occur in parallel or out-of-order. This section contains rules for dealing with nonsequential behavior. These are all considerations that affect ARM10 family processors and later. The precise behavior of any ETM is implementation defined.

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