3.2.1. Direct JTAG access

The Direct JTAG interface is an extension of the ARM TAP controller, and is assigned scan chain number 6. The scan chain consists of a 40-bit shift register comprising:

Only registers 0x000-0x07F can be accessed using Direct JTAG access. The general arrangement of the ETM JTAG registers is shown in Figure 3.1.

Figure 3.1. ETM JTAG structure

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The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored.

A read or a write takes place when the TAP controller enters the UPDATE-DR state.


Direct JTAG access must not be confused with debugger accesses made through the ARM Debug Interface v5, that can also use a JTAG interface.

Restricting Direct JTAG access

Debugger access to the ETM registers can be made read-only by setting bit [22] of the ETMCR, register 0x000. This bit can only be set from software. This bit is not supported in all implementations. See Main Control Register, ETMCR. Tools can determine if a non-JTAG interface is present by reading bit [27] of the ETMCCR. See Configuration Code Register, ETMCCR.

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