3.2.2. Coprocessor access, ETMv3.1 and later

Provision of a coprocessor interface for register access is optional in ETMv3.1 and later. This enables you to use the ETM as an extended breakpoint unit to test for unit failure while testing multiple devices. The coprocessor access also means that you do not have to program each device individually by connecting a probe to each device. You can do the following without external hardware:

This section describes the changes to the programmers’ model, in the following subsections:

Coprocessor models

Where a co-processor model is supported, all the accessible ETM registers are mapped to a single coprocessor. All instructions in Coprocessor 14 with Opcode_1 equal to 1 are reserved for ETM use.

There are two coprocessor models, described in the following sub-sections:

See Behavior of coprocessor accesses for information that applies to both models.

Limited register set model, ETMv3.1 and ETMv3.2 only

The coprocessor model provided in ETMv3.1 and ETMv3.2 provides access to ETM registers 0x000-0x07F only. See The ETM registers for a list of all the ETM registers, in register-number order.

The instructions to read and write the ETM registers are as follows:

MRC <p14>, 1, <Rd>, c0, reg[3:0], reg[6:4]
MCR <p14>, 1, <Rd>, c0, reg[3:0], reg[6:4]

In these instructions, reg[6:0] is the ETM register number.

These instructions have CRn equal to c0 and the register number encoded in Opcode_2 and CRm.

Full access model, ETMv3.3 and later

From ETMv3.3, the coprocessor model provides access to all of the ETM registers, including the CoreSight management registers and the OS Save/Restore registers. See The ETM registers for a list of all the ETM registers, in register-number order.

Note

When accessed through the coprocessor interface, the ETMLAR and ETMLSR, registers 0x3EC and 0x3ED, read-as-zero. You do not have to set a lock to access the ETM registers through the coprocessor interface. In ETMv3.5, coprocessor accesses to the ETMLAR and ETMLSR are unpredictable.

The instructions to read and write the ETM registers are as follows:

MRC <p14>, 1, <Rd>, reg[9:7], reg[3:0], reg[6:4]
MCR <p14>, 1, <Rd>, reg[9:7], reg[3:0], reg[6:4]

In these instructions, reg[9:0] is the ETM register number.

Figure 3.2 shows the mapping between the bits of the ETM register number and the fields of the CP14 instruction.

Figure 3.2. Mapping from register number to CP14 instruction fields

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Behavior of coprocessor accesses

This information applies to both of the coprocessor models. In other words it applies to all ETM register accesses through Coprocessor 14, in ETMv3.1 and later.

Coprocessor access to the ETM registers is only permitted when the ARM processor is in a privileged mode. An attempt to read or write an ETM register using coprocessor instructions while the processor is in User mode results in an Undefined Instruction exception. Coprocessor accesses initiated by a debug tool when the processor is halted in Debug state are always privileged regardless of the state of the CPSR.

In addition, coprocessor access to the ETM registers might be prevented by controls in the processor. The CPACR, NSACR, and HCPTR include controls to trap accesses to ETM registers.

For more information on access permissions see About the access permissions for ETM registers.

Note

This behavior is different to coprocessor access to debug registers, where attempting to access a nonexistent register usually results in an Undefined Instruction exception.

Restricting coprocessor access

Software access to the ETM registers can be made read-only by setting bit [23] of the ETMCR, register 0x000. This bit can only be set by the debugger. See Main Control Register, ETMCR.

Determination of support

To determine whether coprocessor access is supported, read the ETMIDR. See ID Register, ETMIDR, ETMv2.0 and later:

MRC p14, 1, <Rd>, c0, c9, 7

If no Undefined Instruction exception is generated and a nonzero value is returned, then coprocessor access is supported.

Behavior of other CP14 accesses with Opcode_1 equal to 1

All instructions in Coprocessor 14 with Opcode_1 equal to 1 are reserved for ETM use. However, only a limited range of these instructions are used for ETM access. Details are given in the following sub-sections:

ETMv3.1 and v3.2

Only instructions with a CRn value of c0 are used for ETM register accesses. MRC and MCR accesses to Coprocessor 14 with a CRn value greater than 4'b0000 are:

  • undefined in User mode

  • unpredictable in privileged modes.

ETMv3.3 and later

Only instructions with CRn values from 4'b0000 to 4'b0111 are used for ETM register accesses. MRC and MCR accesses to Coprocessor 14 with a CRn value of 4'b1000 or greater are:

  • undefined in User mode

  • unpredictable in privileged modes.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211