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The ETMCIDCMR characteristics are:
Holds a 32-bit mask for use for all Context ID comparisons.
There are no usage constraints.
This register is only implemented from ETMv2.0.
The number of Context ID comparators:
is implementation defined
is specified by ETMCCR bits [25:24]
can be zero.
See Configuration Code Register, ETMCCR.
If the ETM does not implement any Context ID comparators then the ETMCIDCMR is RAZ/WI.
See the register summary in Table 3.3, and Reset behavior.
Figure 3.34 shows the ETMCIDCMR bit assignments:
Table 3.47 shows the ETMCIDCMR bit assignments:
Table 3.47. ETMCIDCMR bit assignments
Bits | Defined in ETM architecture versions | Description |
|---|---|---|
[31:0] | v2.0 and later | Context ID mask value |
The same mask is used for each Context ID comparator. When a Context ID mask bit is set to 1, the corresponding bit in the Value Register is disregarded in the comparison and must be zero.
| Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. | ARM IHI 0014Q |
| Non-Confidential | ID101211 |
| PDF version | |
| Home > Programmers’ Model > Detailed register descriptions > Context ID Comparator Mask Register, ETMCIDCMR |