7.4.2. Normal data packet

The Normal data packet is used for all loads, stores, and CPRT packets that can be output in order. For more information about tracing LSMs see Tracing LSMs.

The ETM compresses the data address trace by reducing the number of bits that are output for the address of the data transfer. The same technique is used as for Branch addresses, where a copy of the last data access address is kept and only the low-order bits that have changed are output for the next address. This is particularly effective, for example, if you are viewing data in one small address range, because all the traced data accesses have the same high-order address bits.

A Normal data packet comprises the following contiguous components:

Normal data packet header

Output first. Always present.

Data address

Present if both of the following conditions are satisfied:

  • data address tracing is enabled in the ETMCR

  • the A bit is set to 1 in the header.

Data addresses consist of one to five bytes. To enable the decompressor to detect the last byte, bit [7] of each byte is set to 1 if there are more address bytes to follow. Bit [7] is LOW in the last address byte. Whether or not data addresses are traced must be statically determined before tracing begins.

The data address is compressed relative to the last traced data address, in a similar manner to instruction addresses. If a data address of any length is traced, bits that are not output are the same as those in the last traced data address.

Data value

Present only if data value tracing is enabled in the ETMCR.

Normal data packets correspond to the most recently-traced data instruction. This is to support processors where instructions that do not perform a data transfer might execute before a previous transfer completes.

Figure 7.32 shows a Normal data packet.

Figure 7.32. Normal data packet for ETMv3.0 and later

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The A bit

The A bit of the Normal data packet header shows that a data address is expected if address tracing is enabled. It is set to 1 for the first data packet output for an LSM, and can be set to 1 for subsequent data packets if their addresses are noncontiguous. In ETMv3.0 a new address must be output if it is noncontiguous and the processor is in Jazelle state. In ETMv3.1 and later this applies to ARM, Thumb, and Jazelle states.


  • In ETMv3.0 you must take account of the instruction type when determining data addresses. This is because the SWP and SWPB instructions perform two accesses to the same address, but only the first has an address output.

  • The A bit can be set to 1 even if address tracing is disabled. In this case the A bit must be ignored and an address is not present.

BE bit

The BE bit shows that the data was a BE-8, ARMv6 and later, big-endian transfer, and that the bytes must be reversed to determine the value that was stored in memory. It represents the state of the E bit in the CPSR at the time of the transfer. See Endian effects and unaligned access.

The BE bit is traced regardless of whether data value tracing is enabled. However, if a data address is traced and this bit is not output because the address is output in less than 5 bytes, then the value of the BE bit is the same as the value given in the last 5-byte data address traced. If the value of the BE bit changes then a full 5-byte data address is output.

Size bits

The size bits are used for data value compression. They specify the size of the transferred data value. Leading zeros are removed from the value as a simple form of this compression. The encoding combinations of the size bits are listed in Table 7.17.

Table 7.17. Size bit encoding combinations

b00Value = 0, no data value bytes follow
b01Value < 256, one data value byte follows
b10Value < 65536, two data value bytes follow
b11No compression done, four data value bytes follow

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