6.7.1. Branch Address trace packets

When a processor performs a branch operation, the destination of the branch is often reasonably close to the current address. The spatial locality of branch destinations provides additional compression of the branch addresses. It is necessary to output only the low order bits that have changed since the last branch or TFO. The full address can be reconstructed when decompression of the trace information takes place.

To decide how many bytes are required, the on-chip logic registers the last branch address that it has output, and when another branch occurs, the new address is compared with the one that was previously output. Only sufficient low order bits must be output to cover all the bits that have changed in the address. For example, if the upper 12 bits of the address are unchanged and A[19] is the most significant bit to have changed, then it is only necessary to output A[19:0]. This can be done in three address packets instead of five.

A full 32-bit address is output over five bytes. When an address is output that is less than 32 bits, the new address value replaces the appropriate bits in the previously output branch address. The value does not have to be added to or subtracted from the previous value, nor is it based on the immediately preceding PC value.

If present, a branch target address is always the last item to be placed into the FIFO on a given cycle. Reason codes are output as part of the TFO packet header, see TFO packet headers.

A branch address can be made up of a maximum of five bytes. Bit [7] is asserted in every byte except the last. This enables the decompressor to detect the last byte of an address.

If an instruction that causes an indirect branch is traced, a branch address packet must be output even if the target of the branch is not traced. This enables the address of the first instruction in any trace gap to be determined. If a branch address packet is output in a cycle in which no instruction is executed, the branch corresponds to the most recent instruction executed. In this case the PIPESTAT is DW, Wait with Data.

Branch address generation

This section describes how a branch address is produced. The sequence is shown in Figure 6.1 for ARM addresses and Figure 6.2 for Thumb addresses.

The address is produced as follows:

  1. The address is prefixed with a 1 in the position of bit [33]. The decompressor uses the position of this bit in the final address to identify whether the code is currently in ARM or Thumb state.

  2. If the packet is an ARM address, it is shifted right by two bits (ARM addresses are word-aligned so the first two bits are always zero).

    If the packet is a Thumb address, it is shifted right by one bit (Thumb addresses are halfword-aligned so the first bit is always zero).

  3. A 1 is added to the end of the packet. This identifies the packet as a branch address.

  4. The value produced (at most 33 bits wide) is divided into 7-bit quantities.

  5. An address continue bit is added to each 7-bit fragment. This bit is set to 1 in all but the last byte of the address packet.

This encoding mechanism means that ARM and Thumb addresses can always be uniquely identified by the high order bits of the fifth address byte.

Figure 6.1. Generating an ARM branch address

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Figure 6.2. Generating a Thumb branch address

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Exception branch addresses

Bit [6] of the fifth byte of an ARM address packet (the E bit) is used to indicate an exception branch address, see Table 6.9. This bit is asserted on any branch that is because of a canceling exception. This enables the decompressor to recognize and inform you that these interrupted instructions were canceled. For more information, see Exceptions.

There is no E bit for Thumb addresses because all exception vectors are executed in ARM state.

Table 6.9. ARM and Thumb 5-byte addresses

ARMThumb
b1XXXXXX1b1XXXXXX1
b1XXXXXXXb1XXXXXXX
b1XXXXXXXb1XXXXXXX
b1XXXXXXXb1XXXXXXX
b0E001XXXb0001XXXX

All encodings of the fifth address byte not specified in Table 6.9 are reserved.

The complete encoding of a full branch address is shown in Figure 6.3.

Note

For future compatibility, when decompressing the trace you must enable the E bit to be set to 1 when branching to any exception vector. The most recent instruction traced is canceled and must be ignored.

Figure 6.3. Full branch address encodings for ARM and Thumb states

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