Glossary

This glossary describes some of the terms used in technical documents from ARM Limited.

Abort

A mechanism that indicates to a core that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. An abort is classified as either a prefetch or data abort, and an internal or external abort.

See Also Data abort, External abort and Prefetch abort.

A-sync

See Alignment synchronization.

Aligned

A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively.

Alignment synchronization (A-sync) header

A sequence of bytes that enables the decompressor to byte-align the trace stream and determine the location of the next header.

Address Packet Offset (APO)

In ETMv1 the Address Packet Offset (APO) is used by the decompressor to synchronize between the pipeline status signals (PIPESTAT) and the trace packet signals (TRACEPKT).

APO

See Address Packet Offset.

ARM instruction

A word that specifies an operation for an ARM processor in ARM state to perform. ARM instructions are word-aligned.

See Also ARM state, Thumb instruction, ThumbEE instruction.

ARM state

An operating state of the processor, in which it executes 32-bit ARM instructions.

See Also ARM instruction, Thumb state, ThumbEE state, Jazelle architecture.

BE-8

Big-endian view of memory in a byte-invariant system.

See Also BE-32, LE, Byte-invariant and Word-invariant.

BE-32

Big-endian view of memory in a word-invariant system.

See Also BE-8, LE, Byte-invariant and Word-invariant.

Big-endian

Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory.

See Also Little-endian and Endianness.

Big-endian memory

Memory in which:

  • a byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address

  • a byte at a halfword-aligned address is the most significant byte in the halfword at that address.

See Also Little-endian memory.

Branch folding

A technique where, on the prediction of most branches, the branch instruction is completely removed from the instruction stream presented to the execution pipeline. Branch folding can significantly improve the performance of branches, taking the CPI for branches below 1.

Branch phantom

The condition codes of a predicted taken branch.

See Also Branch folding.

Branch prediction

The process of predicting if conditional branches are to be taken or not in pipelined processors. Successfully predicting if branches are to be taken enables the processor to prefetch the instructions following a branch before the condition is fully resolved. Branch prediction can be done in software or by using custom hardware. Branch prediction techniques are categorized as static, in which the prediction decision is decided before run time, and dynamic, in which the prediction decision can change during program execution.

Breakpoint

A mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted the programmer to enable inspection of register contents, memory locations, and/or variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested.

See Also Watchpoint.

Byte-invariant

In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access.

The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported. Multi-word accesses are expected to be word-aligned.

See Also Word-invariant.

Context

The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions.

See Also Fast context switch.

Context ID

A 32-bit value accessed through CP15 register 13 that is used to identify and differentiate between different code streams.

CoreSight

The infrastructure for monitoring, tracing, and debugging a complete system on chip.

CPI

See Cycles per instruction.

CPSR

See Current Program Status Register.

Current Program Status Register (CPSR)

The register that holds the current operating processor status.

Cycles Per instruction (CPI)

Cycles per instruction (or clocks per instruction) is a measure of the number of computer instructions that can be performed in one clock cycle. This figure of merit can be used to compare the performance of different CPUs against each other. The lower the value, the better the performance.

Data abort

An indication from a memory system to the core of an attempt to access an illegal data memory location. An exception must be taken if the processor attempts to use the data that caused the abort.

See Also Abort, External abort, and Prefetch abort.

Data instruction

An instruction that passed its condition code test and might have caused a data transfer, for example LDM or MRC.

Data synchronization (D-sync)

Data addresses output in full to enable decompression of partial addresses output in the future.

Debugger

A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

An application that monitors and controls the operation of a second application. Usually used to find errors in the application program flow.

D-Sync

See Data synchronization.

Embedded Trace Buffer (ETB)

The ETB provides on-chip storage of trace data using a configurable sized RAM.

Embedded Trace Macrocell (ETM)

A hardware macrocell that, when connected to a processor, outputs instruction and data trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol.

EmbeddedICE logic

An on-chip logic block that provides TAP-based debug support for ARM processor cores. It is accessed through the TAP controller on the ARM core using the JTAG interface.

Endianness

Byte ordering. The scheme that determines the order in which successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping.

See Also Little-endian and Big-endian.

ETB

See Embedded Trace Buffer.

ETM

See Embedded Trace Macrocell.

Event

1 (Simple): An observable condition that can be used by an ETM to control aspects of a trace.

2 (Complex): A boolean combination of simple events that is used by an ETM to control aspects of a trace.

Event resource

A configurable ETM resource such as an address comparator or a counter. Used when configuring an event.

Exception

A fault or error event that is considered serious enough to require that program execution is interrupted. Examples include attempting to perform an invalid memory access, external interrupts, and undefined instructions. When an exception occurs, normal program flow is interrupted and execution is resumed at the corresponding exception vector. This contains the first instruction of the interrupt handler to deal with the exception.

Exception vector

See Interrupt vector.

External abort

An indication from an external memory system to a core that the value associated with a memory access is invalid. An external abort is caused by the external memory system as a result of attempting to access invalid memory.

See Also Abort, Data abort and Prefetch abort.

Fast Context Switch Extension (FCSE)

Modifies the behavior of an ARM memory system to enable multiple programs running on the ARM processor to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ. From ARMv6, use of the FCSE is deprecated, and the FCSE is optional in ARMv7.

FCSE

See Fast Context Switch Extension. .

Half-rate clocking (in ETM)

Dividing the trace clock by two so that the TPA can sample trace data signals on both the rising and falling edges of the trace clock. The primary purpose of half-rate clocking is to reduce the signal transition rate on the trace clock of an ASIC for very high-speed systems.

I-sync

See Instruction synchronization.

implementation defined

The behavior is not architecturally defined, but must be defined and documented by individual implementations.

implementation specific

The exact behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility.

Imprecise Tracing

A filtering configuration where instruction or data tracing can start or finish earlier or later than expected. Most cases cause tracing to start or finish later than expected.

For example, if TraceEnable is configured to use a counter so that tracing begins after the fourth write to a location in memory, the instruction that caused the fourth write is not traced, although subsequent instructions are. This is because the use of a counter in the TraceEnable configuration always results in imprecise tracing.

See the descriptions of TraceEnable and ViewData in Chapter 2 Controlling Tracing.

Instruction synchronization (I-sync)

Full output of the current instruction address and Context ID on which later trace is based.

Interrupt vector

One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler.

Jazelle architecture

The ARM Jazelle architecture extends the Thumb and ARM operating states by adding a Jazelle state to the processor. Instruction set support for entering and exiting Java applications, real-time interrupt handling, and debug support for mixed Java/ARM applications is present. When in Jazelle state, the processor fetches and decodes Java bytecodes and maintains the Jazelle operand stack.

See Also ARM state, Thumb state, ThumbEE state.

Jazelle RCT (Jazelle Runtime Compiler Target)

An extension to the ARM architecture targeting execution environments, such as Java or .NET Compact Framework. Jazelle RCT provides enhanced support for Ahead-Of-Time (AOT) and Just-In-Time (JIT) compilation. It extends the Thumb instruction set, and introduces a new processor state, ThumbEE.

See Also ThumbEE state.

Joint Test Action Group (JTAG)

The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.

JTAG

See Joint Test Action Group.

LE

Little endian view of memory in both byte-invariant and word-invariant systems.

See Also Byte-invariant and Word-invariant.

Little-endian

Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory.

See Also Big-endian and Endianness.

Little-endian memory

Memory in which:

  • a byte or halfword at a word-aligned address is the least significant byte or halfword in the word at that address

  • a byte at a halfword-aligned address is the least significant byte in the halfword at that address.

See Also Big-endian memory.

Macrocell

A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells (such as a processor, an ETM, and a memory block) plus application-specific logic.

Match

Resources match for one or more cycles when the condition they have been programmed to check for occurs.

Nested Vectored Interrupt Controller (NVIC)

This is an interrupt controller that forms part of the ARMv7-M architecture.

NVIC

See Nested Vectored Interrupt Controller.

P-header

Provides pipeline status information as part of the data stream without using dedicated PIPESTAT signals.

Packet

A number of bytes of related data, consisting of a header byte and zero or more payload bytes.

Packet header

The first byte of an ETM packet that specifies the packet type and how to interpret the following bytes in the packet.

Prefetch abort

An indication from a memory system to the core that an instruction has been fetched from an illegal memory location. An exception must be taken if the processor attempts to execute the instruction. A prefetch abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory.

See Also Data abort, External abort and Abort.

Prohibited region

A period of core execution during which tracing is not permitted, for example because the processor is in Secure state.

RAZ

See Read-As-Zero fields.

Read-As-Zero fields (RAZ)

Appear as zero when read.

Reserved

A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation specific. All reserved bits not used by the implementation must be written as zero and are Read-As-Zero.

SBZP

See Should-Be-Zero-or-Preserved.

Should-Be-Zero-or-Preserved (SZBP)

Must be written as 0, or all 0s for a bit field, by software if the value is being written without having been previously read, or if the register has not been initialized. Where the register was previously read on the same processor, since the processor was last reset, the value in the field should be preserved by writing the value that was previously read.

Hardware must ignore writes to these fields.

If a value is written to the field that is neither 0 (or all 0s for a bit field), nor a value previously read for the same field on the same processor, the result is unpredictable.

TAP

See Test Access Port.

TCD

See Trace capture device.

Test Access Port (TAP)

The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic.

TFO

See Trace FIFO Offset.

Thumb instruction

One or two halfwords that specify an operation for an ARM processor in Thumb state to perform. Thumb instructions must be halfword-aligned. In the original Thumb instruction set, all instructions are 16-bit. Thumb-2 technology, introduced in ARMv6T2, makes it possible to extend the original Thumb instruction set with many 32-bit instructions.

See Also ARM instruction, Thumb state, ThumbEE instruction.

Thumb state

An operating state of the processor, in which it executes 16-bit and 32-bit Thumb instructions.

See Also ARM state, Thumb instruction, ThumbEE state, Jazelle architecture.

ThumbEE instruction

One or two halfwords that specify an operation for an ARM processor in ThumbEE state to perform. ThumbEE instructions must be halfword-aligned.

ThumbEE is a variant of the Thumb instruction set that is designed as a target for dynamically generated code, that is, code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation.

See Also ARM instruction, Thumb instruction, ThumbEE state.

ThumbEE state

An operating state of the processor, in which it executes 16-bit and 32-bit ThumbEE instructions.

See Also ARM state, Thumb state, ThumbEE instruction, Jazelle architecture.

TPA

See Trace Port Analyzer.

Trace capture device (TCD)

A generic term for Trace Port Analyzers, logic analyzers, and Embedded Trace Buffers.

Trace FIFO Offset

ETMv2 generates Trace FIFO Offsets (TFO) to enable the decompressor to synchronize the pipeline status (PIPESTAT) and FIFO output (TRACEPKT) signals. For more information see Trace FIFO offsets.

Trace packet header

Indicates the type of trace packet being output on the TRACEPKT pins, and specifies how to interpret the subsequent bytes of the trace packet.

Trace port

A port on a device, such as a processor or ASIC, that is used to output trace information.

Trace Port Analyzer (TPA)

A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.

Unaligned

A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four.

See Also Aligned.

undefined

Indicates an instruction that generates an Undefined Instruction exception.

unknown

An unknown value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An unknown value must not be a security hole. unknown values must not be documented or promoted as having a defined value or effect.

unpredictable

Means that the behavior of the ETM cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, the only effect of the unpredictable behavior is that the output of that event resource is unknown.

unpredictable behavior can affect the behavior of the entire system, because the ETM can cause the core to enter debug state, and external outputs can be used for other purposes.

Virtual address

Is an address generated by an ARM processor. For processors that implement a Protected Memory System Architecture (PMSA), the virtual address is identical to the physical address

Watchpoint

A watchpoint is a mechanism provided by debuggers to halt program execution when the data contained by a particular memory address is changed. Watchpoints are inserted by the programmer to enable inspection of register contents, memory locations, and variable values when memory is written, to test that the program is operating correctly. Watchpoints are removed after the program is successfully tested.

See Also Breakpoint.

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