Embedded Trace Macrocell Architecture Specification: 3.5.52. OS Lock Status Register, ETMOSLSR, ETMv3.3 and later

The ETMOSLSR characteristics are:

Purpose

Usage constraints

There are no usage constraints.

Configurations

This register is only available in ETMv3.3 or later.

Attributes

See the register summary in Table 3.3, Reset behavior, and the register bit descriptions.

Figure 3.47 shows the ETMOSLSR bit assignments.

Figure 3.47. ETMOSLSR bit assignments

Table 3.61 shows the ETMOSLSR bit assignments.

Table 3.61. ETMOSLSR bit assignments

Bits	Version ^[a]	Description
[31:3]	-	Reserved, Read-As-Zero (RAZ).
[3]	3.5	This bit, in conjunction with bit [0], indicates the level of power down support implemented by the ETM. See Table 3.94.
[2]	3.3	32-bit access required. This bit is always Reads-As-Zero, indicating that 32-bit accesses are required to operate the ETMOSLAR.
[1]	3.3	Locked bit. The possible values of this bit are: 0 ETM trace registers are not locked. 1 ETM trace registers are locked. Any access to these registers returns a slave-generated error response. In ETMv3.5: when the OS Lock is implemented, the OS Lock is always set from an ETM reset reads of this bit return an unknown value when the ETM is powered down, as indicated by bit [0] of the ETMPDSR. See Table 3.94.
[0]	3.3	This bit, in conjunction with bit [3], indicates the level of power down support implemented by the ETM, See Table 3.94.
^[a]The first ETM architecture version that defines the field.

If a read of the ETMOSLSR returns zero, OS Locking is not implemented.

Because Reserved ETM registers Read-As-Zero, this test can be used on ETM versions earlier than ETMv3.3.

See Power Down support for more information about OS Locking.

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