3.5.44. EmbeddedICE Behavior Control Register, ETMEIBCR, ETMv3.4 and later

The ETMEIBCR characteristics are:

Purpose

Controls the sampling behavior of the EmbeddedICE watchpoint comparator inputs.

Usage constraints

There are no usage constraints.

Configurations

This register is only available in ETMv3.4 or later. This is an optional register. Bit [21] of the ETMCCER is set to 1 if the ETMEIBCR is implemented. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

The number of EmbeddedICE watchpoint comparators is implementation defined, and is specified by ETMCCER bits [19:16]. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later. If the ETM implements fewer than eight EmbeddedICE watchpoint comparators the high order bits of the Sampling behavior field are RAZ/WI.

Attributes

See the register summary in Table 3.3 and Reset behavior.

Figure 3.41 shows the ETMEIBCR bit assignments.

Figure 3.41. ETMEIBCR bit assignments

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Table 3.55 shows the ETMEIBCR bit assignments.

Table 3.55. ETMEIBCR bit assignments

Bits

Version [a]

Description

[31:8]-Reserved, Read-as-zero.

[7:0]

v3.4

EmbeddedICE watchpoint input sampling behavior. Each bit controls the sampling behavior of one of the EmbeddedICE watchpoint inputs. Possible values for these bits are:

-0

When sampled, the corresponding input is pulsed for a single sample.

-1

When sampled, the corresponding input is latched and held until one cycle before the next sampling point.

Bit [0] corresponds to input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8.

[a] The first ETM architecture version that defines the field.


For more information about the behavior of the EmbeddedICE watchpoint comparator inputs see Behavior of EmbeddedICE inputs, from ETMv3.4.

Note

From ETMv3.4, if the ETMEIBCR is not implemented, the EmbeddedICE watchpoint comparator inputs must behave as described in Default behavior of EmbeddedICE watchpoint inputs.

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