3.5.56. Integration Mode Control Register, ETMITCTRL, ETMv3.2 and later

The ETMITCTRL register characteristics are:


Enables topology detection or integration testing.

Usage constraints

There are no usage constraints.

  • This register is only available in ETMv3.2 or later.

  • In ETMv3.5 it is implementation defined whether this register is present.


See the register summary in Table 3.3, the register bit descriptions, and Reset behavior.

Figure 3.51 shows the ETMITCTRL register bit assignments.

Figure 3.51.  ETMITCTRL register bit assignments

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Table 3.66 shows the ETMITCTRL register bit assignments.

Table 3.66. ETMITCTRL register bit assignments


Version [a]



When this bit is set to 1, the device enters an integration mode to enable Topology Detection or Integration Testing to be checked.

On an ETM reset this bit is cleared to 0.

[a] The first ETM architecture version that defines the field.

Coprocessor accesses to this register are unpredictable. For other accesses, the response is implementation defined if:

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