3.2.5. ETM register access models

Table 3.1 summarizes the more common ETM register access models, with an indication of the situations when they are likely to be appropriate.

Table 3.1. Typical ETM register access implementations

Register interfacesETM versionsAccess requirements
Direct JTAG onlyAll versionsImplemented where debugger access is required only to registers 0x000 to 0x07F.
Direct JTAG and CoprocessorFrom ETMv3.1Implemented where debugger access is required only to registers 0x000 to 0x07F, and software access to these registers is required.
Coprocessor onlyFrom ETMv3.1

Debugger access is through an ARM Debug Interface v5[a].

In addition, software access is possible.

Direct JTAG and Memory-mappedFrom ETMv3.2Implemented where debugger access is required only to registers 0x000 to 0x07F, and software access to these registers is required.
Memory-mapped onlyFrom ETMv3.2

Debugger access is through an ARM Debug Interface v5[a].

In addition, software access is possible.

[a] For more information see the ARM Debug Interface v5 Architecture Specification.


For information about the access controls that can apply to ETM register accesses see About the access permissions for ETM registers.

For information on power-down support, see Power Down support

When power down support is implemented, the architecture does not permit a Direct JTAG interface to the ETM. Access to the ETM registers from an external debugger must use the ARM Debug Interface v5. For more information, see the ARM Debug Interface v5 Architecture Specification.

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