3.5.54. Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later

The ETMPDSR characteristics are:

Purpose

Indicates the power-down status of the ETM.

Usage constraints
  • For ETMv3.3 and ETMv3.4 there are no usage constraints.

  • In ETMv3.5 this register can only be accessed using a memory-mapped interface or from an external debugger. Coprocessor accesses are unpredictable.

Configurations

This register is only available in ETMv3.3 or later.

Attributes

See the register summary in Table 3.3 and Reset behavior.

Figure 3.49 shows the ETMPDSR bit assignments for ETMv3.5. See Table 3.63 for differences in other ETM versions.

Figure 3.49. ETMPDSR bit assignments

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Table 3.63 shows the ETMPDSR bit assignments for ETMv3.5, and describes the differences in other ETM versions.

Table 3.63. ETMPDSR bit assignments

BitsVersion [a]Description
[31:6]-

Reserved, Read-As-Zero (RAZ).

[5]-

Reserved, Read-As-Zero (RAZ)

3.5

OS lock status. The value of this bit is the same as the value of bit [1] of the ETMOSLSR, which indicates whether the ETM trace registers are locked. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later.

This bit is unknown when the ETM is powered down

[4:2]-Reserved, Read-As-Zero (RAZ).
[1]3.3

Sticky Register state bit. The possible values of this bit are:

0

ETM Trace Registers have not been powered down since this register was last read.

1

ETM Trace Registers have been powered down since this register was last read, and have lost their state.

When the core power domain of the ETM is powered down or reset, this bit is set to 1.

Reads of this register when the core power domain is powered down or held in reset return 1 for this bit, and do not change the value of this bit.

Reads of this register when the core power domain is powered up and not held in reset return the current value of this bit, and then clear this bit to 0. If the Software Lock mechanism is locked and the ETMPDSR read is made through the memory mapped interface, this bit is not cleared.

In ETMv3.3 and ETMv3.4,when this bit is set, accesses to any ETM Trace Registers return an error response.

In ETMv3.5, the value of this bit has no effect on accesses to the ETM Trace Registers.

[0]3.3

ETM powered up bit. The value of this bit indicates whether you can access the ETM Trace Registers. The possible values are:

0

ETM Trace Registers cannot be accessed.

1

ETM Trace Registers can be accessed.

When this bit is set to 0, accesses to any ETM Trace Registers return an error response.

[a] The first ETM architecture version that defines the field.


Table 3.64 shows the different encodings of ETMPDSR bits [1:0].

Table 3.64. ETMPDSR encodings

Bit [1] Sticky Register stateBit [0] ETM powered upMeaning
00ETM Trace Registers are inaccessible. No state has been lost.
01ETM Trace Registers are accessible.
10ETM Trace Registers are powered down, inaccessible, and their state has been lost.
11ETM Trace Registers are powered up. However, their state has been lost because of a power down.

If the ETM only occupies a single power domain, this register might always read as 0x00000001, indicating that the ETM is powered up and accessible. In this case, if the ETM is not powered up:

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