7.5.2. Instructions that can be paused for continuation

In other ARM processor architectures, there are two ways of responding to an interrupt that occurs during the execution of an LSM instruction:

See Load/Store Multiple (LSM) instructions for details of the instructions to which this applies.

In the ARMv7-M architecture, LSM instructions can be paused for continuation during execution. When this happens:

When an instruction is paused, trace output is generated both when the exception occurs and again when execution of the instruction is resumed. Extended branch with exception packets are generated at both points, even though no exception occurs when execution is resumed. These packets are described in Extended Exception handling in Instruction-only trace. In summary:

Tracing continuation of an instruction during instruction-only trace

In instruction-only trace, there is no tracing of the resumed instruction. With instruction-only trace:

  • When the exception occurs, the paused instruction is traced as canceled by the exception branch packet.

  • The return from the exception handler is traced as a normal branch, to the instruction that follows the paused instruction in the program execution flow. No Exception information bytes are output.

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