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| Home > ETMv3 Signal Protocol > Behavior of EmbeddedICE inputs, from ETMv3.4 > Implementation of pulse and latch behavior of EmbeddedICE inputs | |||
Correct implementation of configurable EmbeddedICE watchpoint comparator inputs requires control signals that indicate the sampling point for each input. For each input, the input is sampled at the appropriate point indicated by the control signals. The sampling depends on the value of the corresponding bit in the ETMEIBCR. If this bit is:
If the signal is sampled HIGH, the EmbeddedICE input is asserted for a single cycle from the point where it is sampled.
The EmbeddedICE signal is latched to the sampled value, and held until the cycle before the next sample point.