7.9. Behavior of EmbeddedICE inputs, from ETMv3.4

In ETMv3.3 and earlier, if an ETM implementation supported EmbeddedICE watchpoint comparator inputs then it provided two EmbeddedICE inputs. From ETMv3.4, the number of EmbeddedICE watchpoint comparator inputs is implementation defined, between 0 and 8, and is indicated by bits [19:16] of the ETMCCER, see Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

In addition, ETMv3.4 defines an optional read/write register that permits dynamic control of the behavior of the EmbeddedICE watchpoint comparator inputs, see EmbeddedICE Behavior Control Register, ETMEIBCR, ETMv3.4 and later. Bit [21] of the ETMCCER is set to 1 when the ETMEIBCR is implemented. ETMv3.4 also specifies default behavior of the EmbeddedICE watchpoint inputs, in different contexts, that must be implemented when the ETMEIBCR is not implemented. For more information, see Default behavior of EmbeddedICE watchpoint inputs.

Additional information about the behavior of the EmbeddedICE inputs is given in the following sections:

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